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Compressing three-dimensional sparse arrays using inter- and intra-task parallelization strategies on Intel Xeon and Xeon Phi

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Abstract

Array operations are useful in a lot of scientific codes. In recent years, several applications, such as the geological analysis and the medical images processing, are processed using array operations for three-dimensional (abbreviate to “3D”) sparse arrays. Due to the huge computation time, it is necessary to compress 3D sparse arrays and use parallel computing technologies to speed up sparse array operations. How to compress the sparse arrays efficiently is an important task for practical applications. Hence, in this paper, two strategies, inter- and intra-task parallelization (abbreviate to “ETP” and “RTP”), are presented to compress 3D sparse arrays, respectively. Each strategy was designed and implemented on Intel Xeon and Xeon Phi, respectively. From experimental results, the ETP strategy achieves 17.5\(\times \) and 18.2\(\times \) speedup ratios based on Intel Xeon E5-2670 v2 and Intel Xeon Phi SE10X, respectively; 4.5\(\times \) and 4.5\(\times \) speedup ratios for the RTP strategy based on these two environments, respectively.

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Acknowledgments

Part of this work was supported by the Ministry of Science and Technology under the Grants MOST104-2221-E-182-050, MOST104-2221-E-182-051 and MOST103-2221-E-126-013. The authors would like to thank the hardware support by the Professor Che-Rung Lee who joined the Department of Computer Science at National Tsing Hua University. The authors also would like to thank other experts who discussed with us in the past.

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Authors and Affiliations

  1. Department of Computer Science and Information Engineering, Chang Gung University, Taoyuan, 33302, Taiwan

    Chun-Yuan Lin & Huang Ting Yen

  2. Department of Computer Science and Communication Engineering, Providence University, Taichung, 43301, Taiwan

    Che-Lun Hung

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  1. Chun-Yuan Lin
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  2. Huang Ting Yen
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  3. Che-Lun Hung
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Correspondence to Che-Lun Hung.

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Lin, CY., Yen, H.T. & Hung, CL. Compressing three-dimensional sparse arrays using inter- and intra-task parallelization strategies on Intel Xeon and Xeon Phi. J Supercomput 73, 3391–3410 (2017). https://doi.org/10.1007/s11227-016-1820-x

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  • DOI: https://doi.org/10.1007/s11227-016-1820-x

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