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Hardware coprocessors for high-performance symmetric cryptography

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Abstract

This work presents two hardware coprocessors for high-performance symmetric cryptographic algorithms. Two algorithms have been implemented, that is, Advanced Encryption Standard Algorithm and International Data Encryption Algorithm, using two different hardware coprocessors, a field-programmable gate array (FPGA) and a graphics processing unit (GPU). These two devices allow implementing very fast versions of both cryptographic algorithms employing two different parallelism methodologies: hardware parallelism in the FPGA implementations and multicore parallelism in GPU implementations.

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Notes

  1. Group of threads physically executed in parallel (SIMD) on an SM.

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Acknowledgements

This work was partially funded by the Spanish Ministry of Economy and Competitiveness and the ERDF (European Regional Development Fund), under the contract TIN2016-76259-P (PROTEIN project). This work was partially supported by the computing facilities of Extremadura Research Centre for Advanced Technologies (CETA-CIEMAT), funded by the European Regional Development Fund (ERDF). CETA-CIEMAT belongs to CIEMAT and the Government of Spain [55]. Special thanks to Juan M. Sánchez-Pérez without whom this work would not have been possible.

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  1. Department of Technologies of Computers and Communications, University of Extremadura, Escuela Politécnica, Campus Universitario S/N, 10003, Cáceres, Spain

    José M. Granado-Criado & Miguel A. Vega-Rodríguez

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  1. José M. Granado-Criado
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  2. Miguel A. Vega-Rodríguez
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Correspondence to José M. Granado-Criado.

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Granado-Criado, J.M., Vega-Rodríguez, M.A. Hardware coprocessors for high-performance symmetric cryptography. J Supercomput 73, 2456–2482 (2017). https://doi.org/10.1007/s11227-016-1929-y

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