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Title: A performance study of the time-varying cache behavior: a study on APEX, Mantevo, NAS, and PARSEC

Journal Article · · Journal of Supercomputing
 [1];  [2];  [1];  [3]
  1. New Mexico State Univ., Las Cruces, NM (United States). Klipsch School of Electrical and Computer Engineering
  2. Los Alamos National Lab. (LANL), Los Alamos, NM (United States)
  3. Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
+ Show Author Affiliations

Cache has long been used to minimize the latency of main memory accesses by storing frequently used data near the processor. Processor performance depends on the underlying cache performance. Therefore, significant research has been done to identify the most crucial metrics of cache performance. Although the majority of research focuses on measuring cache hit rates and data movement as the primary cache performance metrics, cache utilization is significantly important. We investigate the application’s locality using cache utilization metrics. In addition, we present cache utilization and traditional cache performance metrics as the program progresses providing detailed insights into the dynamic application behavior on parallel applications from four benchmark suites running on multiple cores. We explore cache utilization for APEX, Mantevo, NAS, and PARSEC, mostly scientific benchmark suites. Our results indicate that 40% of the data bytes in a cache line are accessed at least once before line eviction. Also, on average a byte is accessed two times before the cache line is evicted for these applications. Moreover, we present runtime cache utilization, as well as, conventional performance metrics that illustrate a holistic understanding of cache behavior. To facilitate this research, we build a memory simulator incorporated into the Structural Simulation Toolkit (Rodrigues et al. in SIGMETRICS Perform Eval Rev 38(4):37–42, 2011). Finally, our results suggest that variable cache line size can result in better performance and can also conserve power.

Research Organization:
Los Alamos National Laboratory (LANL), Los Alamos, NM (United States); Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Organization:
USDOE Laboratory Directed Research and Development (LDRD) Program; U.S. Army Research Laboratory (ARL); National Science Foundation (NSF)
Grant/Contract Number:
AC52-06NA25396; W911NF-07-2-0027; AC04-94AL85000
OSTI ID:
1394977
Alternate ID(s):
OSTI ID: 1399561
Report Number(s):
LA-UR-17-24198; SAND-2017-8114J
Journal Information:
Journal of Supercomputing, Vol. 74, Issue 2; ISSN 0920-8542
Publisher:
SpringerCopyright Statement
Country of Publication:
United States
Language:
English
Citation Metrics:
Cited by: 1 work
Citation information provided by
Web of Science

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97 MATHEMATICS AND COMPUTING
Cache Utilization
Locality
Workload Characterization
Cache Line Utilization
Multicore Cache Simulation
Runtime Evaluation
Scratchpad
Cache utilization
Workload characterization
Cache line utilization
Multicore cache simulation
Runtime evaluation