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Efficient design and hardware implementation of the OpenFlow v1.3 Switch on the Virtex-6 FPGA ML605

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Abstract

Software-defined network (SDN) has had the evolution of the current network with the aim of removing its restrictions so that the data plane has been separated from its control plane. In the architecture of the SDN, the most controversial device is the OpenFlow Switch in that in the OpenFlow Switch, it is packets which are processed and investigated. Now, OpenFlow Switch versions 1.0 and 1.1 have been implemented on hardware platforms and support limited specifications of the OpenFlow. The present article is to design and implement the architecture of the OpenFlow v1.3 Switch on the \(\hbox {Virtex}{\textregistered }\)-6 FPGA ML605 board because the FPGA platform has high flexibility, processing speed and reprogrammability. Although little research investigated performance parameters of the OpenFlow Switch, in the present study, the OpenFlow system (switch and controller) is to be implemented on the FPGA via the VHDL on the one hand, and performance parameters of the OpenFlow Switch and its stimulation performance is to be investigated via the ISE design suite on the other hand. In addition to enjoying high flexibility, this architecture has a consumer hardware at the level of other start-ups. The main advantage of the proposed design is that it increases the speed of packet pipeline processing in flow tables switch. Besides, it supports the features of the OpenFlow v1.3. Its parser supports 40 packet headers in the network and provides the possibility of switch development for next versions of the OpenFlow as easily as possible.

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Authors and Affiliations

  1. Faculty of Computer Engineering, University of Isfahan, Isfahan, Iran

    Abbas Yazdinejad, Ali Bohlooli & Kamal Jamshidi

Authors
  1. Abbas Yazdinejad
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  2. Ali Bohlooli
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  3. Kamal Jamshidi
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Correspondence to Ali Bohlooli.

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Yazdinejad, A., Bohlooli, A. & Jamshidi, K. Efficient design and hardware implementation of the OpenFlow v1.3 Switch on the Virtex-6 FPGA ML605. J Supercomput 74, 1299–1320 (2018). https://doi.org/10.1007/s11227-017-2175-7

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  • DOI: https://doi.org/10.1007/s11227-017-2175-7

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