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REPLICA MBTAC: multithreaded dual-mode processor

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Abstract

Prevailing trend in design of chip multiprocessors (CMP) has been that single-core processors are replicated. Therefore, they typically define asynchronous computational model, require heavily locality-aware memory allocation, and present high overheads in intercommunication. This kind of properties make parallel programming very challenging and prone to errors. We introduce our new dual-mode MultiBunched/Threaded Architecture with Chaining (MBTAC) processor core, the main building block of the REPLICA CMP. It provides a modern, sophisticated way for writing general purpose parallel programs backed up by native execution capabilities/realization of key concepts. These include support for cost-efficient machine instruction-level synchronization and uniform shared global memory for enabling easy-to-program memory allocation of data structures and data movement. MBTAC makes use of low-overhead thread-context switching solution; it has parallel computing savvy functional unit organization to exploit inter-thread instruction-level parallelism and highly efficient multioperations. To evaluate the goodness of our proposal, we implemented three MBTAC constellations featuring up to 2048 parallel threads on FPGA, compared it with respect to DLX and Intel’s Core i7 processors. The results point toward high performance in communication-intensive problems, simplified parallel programmability, and regular, implementation-friendly structure.

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Notes

  1. This paper in an extended version of the paper [9] with more detailed description of the MBTAC processor, inclusion of MBTAC for 16-core constellations in FPGA prototype description and evaluation section, and measurements and results. It extends also theoretical work [7] that used a weakly implementable development version of the ECLIPSE architecture [5] for the tests.

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Acknowledgements

This work was funded by VTT, the Grant 289773 of Academy of Finland and the Celtic-Plus Project CONVINcE.

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Authors and Affiliations

  1. Computing Platforms Team, VTT, Box 1100, 90571, Oulu, Finland

    Martti Forsell & Jussi Roivainen

  2. Department of Information Technology, University of Turku, 20014, Turku, Finland

    Ville Leppänen

Authors
  1. Martti Forsell
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  2. Jussi Roivainen
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  3. Ville Leppänen
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Correspondence to Martti Forsell.

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Forsell, M., Roivainen, J. & Leppänen, V. REPLICA MBTAC: multithreaded dual-mode processor. J Supercomput 74, 1911–1933 (2018). https://doi.org/10.1007/s11227-017-2199-z

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  • DOI: https://doi.org/10.1007/s11227-017-2199-z

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