High-performance ECC processor architecture design for IoT security applications

Abstract

In recent years, the usage of elliptic curve cryptography (ECC) in IoT applications is steadily increasing. The end nodes in IoT applications demand optimized device performance in terms of reduced power consumption and improved computing speed while not compromising on the security of the connected devices. ECC provides better security standards compared with many conventional cryptographic algorithms providing further scope to optimize the performance parameters. This work focuses on improving the key parameters like computing speed, area required for hardware implementation of ECC and demonstrates an efficient way of using the hardware resource sharing and scheduling mechanisms in elliptic curve group operations in affine coordinates which is crucial for implementation of scalar multiplication over prime field $\mathbb {F}_{p}$. With the proposed scalar multiplication hardware architecture, we have achieved a good area-delay product and a significant reduction in cycle count when compared with other reported designs using the same affine coordinates. The proposed architecture has been implemented with 256 bits in both Xilinx Kintex-7 and Virtex-7 FPGA devices. The FPGA synthesis results show that a throughput of 68.52 kbps at a clock frequency of 124.2 MHz is achieved for $\mathbb {F}_{256}$ and the computation time is reduced around 1 ms without using any DSP slices.