Skip to main content
SpringerLink
Log in

NVM Streaker: a fast and reconfigurable performance simulator for non-volatile memory-based memory architecture

  • Published:
The Journal of Supercomputing Aims and scope Submit manuscript

Abstract

The high density, low power consumption non-volatile memory (NVM) provides a promising DRAM alternative for the in-memory big-data processing applications, e.g., Spark, It is significant to simulate the behaviors when NVMs are deployed into the area of big-data processing before their widespread use in market. However, existing simulation approaches are not applicable for big-data processing due to two reasons. First, some approaches require complicated hardware and/or OS supports. Second, cycle-level or function-level simulations are too time-consuming to simulate the whole software stack of big-data processing. Therefore, the complexity and expensive time cost in NVM simulation have dramatically dragged down the integrated research of big data with NVM. This paper proposes a fast and reconfigurable simulation method, called NVM Streaker, which does not need complex hardware or OS supports. It simulates NVM access costs using disturbed DRAM accesses and commonly configurable hardware parameters. It is fast since we use DRAM accesses and change its access costs to simulate NVM access costs, thus enabling to simulate the whole software stack to run Spark applications. It is reconfigurable since we enable users to configure the disturbed memory access costs, in order to simulate different NVM access costs. The experimental results show that we can simulate Spark applications with almost negligible cost and high efficiency.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12

Similar content being viewed by others

References

  1. Atkinson MP, Bailey PJ, Chisholm KJ et al (1983) An approach to persistent programming. Computer Journal 26(4):360–365

    Article  MATH  Google Scholar 

  2. Atkinson MP, Daynes L, Jordan MJ et al (1996) An orthogonally persistent java. SIGMOD Rec 25(4):68–75

    Article  Google Scholar 

  3. Agarwal N, Nellans D, Stephenson M et al (2015) Page placement strategies for GPUs within heterogeneous memory systems. In Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, ACM, pp 607–618

  4. BjÃÿrling M, Madsen J, Bonnet P et al (2014) LightNVM: lightning fast evaluation platform for non-volatilememories. In: 5th Annual Non-Volatile Memories Workshop

  5. Caulfield AM, Coburn J, Mollov T et al (2010) Understanding the impact of emerging non-volatile memories on high-performance, IO-intensive computing. In: Proceedings of the 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis, 13–19 Nov 2010, pp 1–11

  6. DeBrabant J, Arulraj J, Pavlo A et al (2014) A prolegomenon on OLTP database systems for non-volatile memory. In: ADMS@VLDB, pp 57–63

  7. Dhiman G, Ayoub R, Rosing T (2009) PDRAM: a hybrid PRAM and DRAM main memory system. In: Proceedings of the 46th Annual Design Automation Conference (DAC’09), pp 664–669

  8. Dong X, Jouppi N, Xie Y (2012) Nvsim: a circuit-level performance, energy, and area model for emerging nonvolatile memory. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp 994–1007

  9. Dulloor SR, Kumar S, Keshavamurthy A et al (2014) System software for persistent memory. In: Proceedings of EuroSys

  10. Hu J, Xue C, Tseng W et al (2010) Minimizing write activities to non-volatile memory via scheduling and recomputation. In: Proceedings of 2010 IEEE 8th Symposium on Application Specific Processors (SASP), pp 101–106

  11. Hu J, Xue C, Zhuge Q, Tseng WC et al (2011) Towards energy efficient hybrid on-chip scratch pad memory with nonvolatile memory. In: Proceedings of Design, Automation Test in Europe Conference and Exhibition (DATE), Mar 2011, pp 1–6

  12. Hu J, Xue CJ et al (2012) Scheduling to optimize cache utilization for non-volatile main memories. In: IEEE Transactions on Computers (TC), Dec 2012

  13. Hu X, Eleftherou E, Haas et al R (2009) Write amplification analysis in flash-based solid state drives. In: Proceedings of SYSTOR 2009: The Israeli Experimental Systems Conference

  14. Lee B, Ipek E, Mutlu O et al (2009) Architecting phase change memory as a scalable dram alternative. In: Proceedings of the 36th International Symposium on Computer Architecture, 2009

  15. Lee BC, Ipek E, Mutlu O, Burger D (2007) Architecting phase change memory as a scalable DRAM alternative. In Proceedings of ISCA 36, June 2007

  16. Liu D, Zhong K, Wang T, Wang Y, Shao Z, Sha EHM, Xue J (2016) Durable address translation in PCM-based flash storage systems. In: IEEE Transactions on Parallel and Distributed Systems (TPDS)

  17. Li Q, Zhao Y, Hu J et al (2012) MGC: multiple graph-coloring for non-volatile memory based hybrid scratchpad memory. In: Proceedings of 16th Workshop on Interaction Between Compilers and Computer Architectures (INTERACT), Feb 2012, pp 17–24

  18. Liu T, Zhao Y, Xue C et al (2011) Power-aware variable partitioning for DSPS with hybrid pram and dram main memory. In: Proceedings of 48th ACM/EDAC/IEEE Design Automation Conference (DAC), June 2011, pp 405–410

  19. Lu Y, Shu J, Zheng W (2013) Extending the lifetime of flash-based storage through reducing write. In: The 11th USENIX Conference on File and Storage Technologies

  20. Malicevic J, Dulloor S, Sundaram N et al (2015) Exploiting NVM in large-scale graph analytics. In: INFLOW’15

  21. Mars J, Tang L, Hundt R et al Bubble-up: increasing utilization in modern warehouse scale computers via sensible co-locations. In: Proceedings of Micro’11, Dec 2011, pp 248–259

  22. Mogul JC, Argollo E, Shah M et al (2009) Operating system support for NVM + DRAM hybrid main memory. In: Hot Topics in Operating Systems

  23. Manchanda N, Anand K (2010-05-04) Non-Uniform Memory Access (NUMA). http://cs.nyu.edu/~lerner/spring10/projects/NUMA.pdf. New York University. Retrieved 27 Jan 2014

  24. Mangalagiri P, Sarpatwari K, Yanamandra A et al (2008) A low-power phase change memory based hybrid cache architecture. In: Proceedings of 18th ACM Great Lakes Symposium on VLSI, pp 395–398

  25. Oh Y, Choi J, Lee D et al (2013) Caching less for better performance: balancing cache size and update cost of flash memory cache in hybrid storage systems. In: Proceedings of the 10th USENIX Conference on File and Storage Technologies (FAST’12), pp 25–25

  26. Poremba M, Xie Y (2012) Nvmain: an architectural-level main memory simulator for emerging non-volatile memories. In: Proceedings of IEEE Computer Society Annual Symposium on VLSI, Aug 2012, pp 392–397

  27. Poremba M, Zhang T, Xie Y (2015) NVMain 2.0: a user-friendly memory simulator to model (non-)volatile memory systems. Comput Archit Lett 14(2):140–143

    Article  Google Scholar 

  28. Qureshi M, Srinivasan V, Rivers JA (2009) Scalable high performance main memory system using phase-change memory technology. In: Proceedings of the 36th International Symposium on Computer Architecture, 2009

  29. Qureshi MK, Franceschini MM, Lastras-montao LA (2010) Improving read performance of phase change memories via write cancellation and write pausing. In: Proceedings of 16th International Symposium on High-Performance Computer Architecture, 2010

  30. Sengupta D, Wang Q et al (2015) A framework for emulating non-volatile memory systems with different performance characteristics. In: Proceedings of ICPE’14, 2015

  31. Soundararajan G, Prabhakaran V, Balakrishnan M et al (2010) Extending SSD lifetimes with disk-based write caches. In: Proceedings of the 8th USENIX Conference on File and Storage Technologies (FAST’10), pp 8–8

  32. Tseng W, Xue C, Zhuge Q et al (2010) Optimal scheduling to minimize non-volatile memory access time with hardware cache. In: Proceedings of 18th IEEE/IFIP VLSI System on Chip Conference (VLSI-SoC), pp 131–136

  33. Uttamchandani S (2015) Scale out storage architectures in the NVM Era, evolution or revolution? Flashmemory Summit, Santa Clara, CA

  34. Volos H, Tack AJ, Swift MM (2011) Mnemosyne: lightweight persistent memory. In: Proceedings of the Sixteenth International Conference on Architectural Support for Programming Languages and Operating Systems, March 05–11, 2011, Newport Beach, California, USA https://doi.org/10.1145/1950365.1950379

  35. Wang C, Cao T, Zigman J, Lv F, Zhang Y, Feng X (2016). Efficient management for hybrid memory in managed language runtime. In: Proceedings of Network and Parallel Computing

  36. Wang D, Ganesh B, Tuaycharoen N et al (2005) DRAMsim: a memory system simulator. SIGARCH Comput Archit News 33(4):100–107

    Article  Google Scholar 

  37. Wei W, Jiang D, Chen M (2014) Exploring opportunities for non-volatile memories in big data applications. In: Big Data Benchmarks, Performance Optimization, and Emerging Hardware. Springer, Berlin, pp 209–220

  38. Wilton SJE, Jouppi NP (1996) CACTI: an enhanced cache access and cycle time model. IEEE J Solid-State Circuits 31(5):677–688

    Article  Google Scholar 

  39. Wu X, Li J, Zhang L, Speight E et al (2009) Power and performance of read-write aware hybrid caches with non-volatile memories. In: Design, Automation and Test in Europe Conference and Exhibition, IEEE, pp 737–742

  40. Wu X, Li J, Zhang L, Speight E et al (2009) Hybrid cache architecture with disparate memory technologies. SIGARCH Comput Archit News 37(3):34–45. https://doi.org/10.1145/1555815.1555761=0pt

    Article  Google Scholar 

  41. Wang Y, Wang T, Liu D, Shao Z, Xue Jingling (2017) Fine grained, direct access file system support for storage class memory. J Syst Archit 72:80–92

    Article  Google Scholar 

  42. Wang Y, Wang T, Shao Z, Liu D, Xue J (2015) File system-independent block device support for storage class memory. In: The International Workshop of Software-Defined Data Communications And Storage (SDDCS) 2015, in Conjunction with IEEE INFOCOM 2015, Hongkong

  43. Xue C, Zhang Y, Chen Y et al (2011) Emerging non-volatile memories: opportunities and challenges. In: Proceedings of 9th International Conference on Hardware/Software Codesign and System Synthesis (CODES +ISSS), Oct 2011, pp 325–334

  44. Yang H, Breslow A, Mars J et al (2013) Bubble-flux: precise online QoS management for increased utilization in warehouse scale computers. In: International Symposium on Computer Architecture 2013

  45. Zhou P, Zhao B, Yang J et al (2009) A durable and energy efficient main memory using phase change memory technology. In: Proceedings of the 36th International Symposium on Computer Architecture

  46. http://spark.apache.org/

  47. https://www.mathworks.com/help/matlab/getting-started-with-matlab.html

  48. http://www.m5sim.org/Main_Page

  49. https://eng.umd.edu/~blj/dramsim/

Download references

Author information

Authors and Affiliations

  1. State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China

    Danqi Hu, Fang Lv, Chenxi Wang, Hui-Min Cui, Lei Wang, Ying Liu & Xiao-Bing Feng

  2. University of Chinese Academy of Sciences, No. 19(A) Yuquan Road, Shijingshan District, Beijing, China

    Danqi Hu, Chenxi Wang, Hui-Min Cui & Xiao-Bing Feng

Authors
  1. Danqi Hu
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Fang Lv
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Chenxi Wang
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Hui-Min Cui
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Lei Wang
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. Ying Liu
    View author publications

    You can also search for this author in PubMed Google Scholar

  7. Xiao-Bing Feng
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Fang Lv.

Additional information

This research is supported by National Key R&D Program of China under Grants Nos. 2016YFB1000402, 2016YFB1000200 and 2016YFB0200504; the NSFC under Grants Nos. 61521092, 61672492, 61303053, 61432016 and 61402445.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Hu, D., Lv, F., Wang, C. et al. NVM Streaker: a fast and reconfigurable performance simulator for non-volatile memory-based memory architecture. J Supercomput 74, 3875–3903 (2018). https://doi.org/10.1007/s11227-018-2438-y

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11227-018-2438-y

Keywords

Search

Navigation