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Wasted dynamic power and correlation to instruction set architecture for CPU throttling

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Abstract

Reducing dynamic power consumption is one of the major design goals in modern high-performance processor design. Throttling is a mechanism that reduces dynamic power at the expense of reduced throughput. Instruction profiling can identify a set of instructions suitable for fine-grained throttling without significant performance degradation. In this paper, an Electronic Design Automation (EDA) flow was developed to process pipeline trace at an early stage to identify the bottleneck. Using the developed EDA flow, this work identifies a set of instructions suitable for fine-grained CPU throttling to reduce wasted dynamic power in RISC-V architecture. To rank higher stall causing instructions in the instruction profile, a weight-based system was introduced. It was observed that independent of the workload and type, higher stall causing instructions were repeating across all the benchmark programs. The top 10 instruction profiles for each test suite identify probable throttling clock cycles for each pipeline stage for wasted dynamic power reduction at minimal performance loss. These results are expected to enable researchers to reduce wasted dynamic power by modifying existing architecture and effectively apply throttling mechanism without significant performance degradation.

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  1. Abdullah A. Owahid & Eugene B. John

    Present address: , One UTSA Circle, San Antonio, TX, 78249, USA

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, The University of Texas at San Antonio, San Antonio, TX, USA

    Abdullah A. Owahid & Eugene B. John

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  1. Abdullah A. Owahid
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  2. Eugene B. John
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Correspondence to Abdullah A. Owahid.

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Owahid, A.A., John, E.B. Wasted dynamic power and correlation to instruction set architecture for CPU throttling. J Supercomput 75, 2436–2454 (2019). https://doi.org/10.1007/s11227-018-2637-6

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  • DOI: https://doi.org/10.1007/s11227-018-2637-6

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