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Time-sensitivity-aware shared cache architecture for multi-core embedded systems

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Abstract

In embedded systems such as automotive systems, multi-core processors are expected to improve performance and reduce manufacturing cost by integrating multiple functions on a single chip. However, inter-core interference in shared last-level cache (LLC) results in increased and unpredictable execution times for time-sensitive tasks (TSTs), which have (soft) timing constraints, thereby increasing the deadline miss rates of such systems. In this paper, we propose a time-sensitivity-aware dead block-based shared LLC architecture to mitigate these problems. First, a time-sensitivity indication bit is added to each cache block, which allows the proposed LLC architecture to be aware of instructions/data belonging to TSTs. Second, portions of the LLC space are allocated to general tasks without interfering with TSTs by developing a time-sensitivity-aware dead block-based cache partitioning technique. Third, to reduce the deadline miss rate of TSTs further, we propose a task matching in shared caches and a cache partitioning scheme that considers the memory access characteristics and the time-sensitivity of tasks (TATS). The TATS is combined with our proposed dead block-based scheme. Our evaluation shows that the proposed schemes reduce deadline miss rates of TSTs compared to conventional shared caches. On a dual-core system, compared to a baseline, equal partitioning, and state-of-the-art quality-of-service-aware cache partitioning, our proposed dead block-based cache partitioning provides 9.3%, 30.5%, and 2.6% lower average deadline miss rates, respectively. On a quad-core system, compared to the baseline, equal partitioning, and state-of-the-art quality-of-service-aware cache partitioning, the combination of our proposed schemes provides 21.2%, 17.7%, and 4.1% lower average deadline miss rates, respectively.

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Notes

  1. In this study, we do not consider applications having hard timing constraints, such as engine control and power train, which require very strict timing constraints. We focus on the applications that can tolerate some deadline misses, which are called time-sensitive applications in this paper and [12].

  2. The task categorization is dependent on the timing requirement of the task. If a task is periodically executed and has a (soft) deadline, the task would be categorized as a TST. For example, if there is a video decoding application that requires a frame rate of 30 fps, the video decoding task of the application can be considered as a TST because it is periodically executed and must be accomplished within 33 ms to achieve the required frame rate. On the other hand, if a task has no deadline but requires higher overall performance, the task would be categorized as a GT.

  3. In this paper, performance predictability is defined as the inverse of the difference between the shortest and longest execution times of a task. A higher-performance predictability of a task indicates a smaller performance variation and better tail performance of the task.

  4. In this paper, a TST of an application is defined as the core task that runs periodically and has soft timing constraints. A job is defined as an instance of the TST. A detailed model is presented in Sect. 4, and our evaluation methodology is similar to [27].

  5. We do not consider tasks having hard timing constraints in this paper.

  6. We assume high utilization to examine the impact of inter-core cache interference. High utilization is preferred for lower manufacturing cost of the system.

  7. In this study, we allocate equal size cache partitions to TSTs. However, the cache space is not wasted because the actual cache partitioning is dynamically done during runtime. When some tasks are idle, the other tasks can occupy their cache space.

  8. The parameters are also used in Algorithms 3 and 4.

  9. This is because the maximum number of parallel tasks in a multi-core system is equal to the number of cores. The maximum number of groups is equal to that of cores when only TSTs are running.

  10. If the number of cache partitions cannot be divided by that of current groups (e.g., 16 partitions shared by 3 groups), the remaining partitions are randomly allocated to the groups.

  11. The number of cores used in this paper is at most 4. Therefore, 2-bit group field is used in this paper. Even with 64 cores, only 6 bits are needed.

  12. \(t_{CL}\): CAS (Column Address Strobe) latency, \(t_{RCD}\): row address to column address delay, \(t_{RP}\): row precharge time.

  13. In the experiments, we used configurations to fit the working sets of MiBench benchmarks and to model the inter-core cache interference in a harsh situation.

  14. In this paper, we profile the benchmarks with a halved LLC. For more partitions, one can profile the tasks with LLCs that are partitioned into more than two segments. Nevertheless, halving LLC space can be a good estimator for the performance sensitivities of tasks. Similar categorization is used in [46].

  15. To estimate the probability density of the execution times, kernel density estimation is applied to the data. For kernel function of the estimation, we used normal kernel function which implies that the probability of sampled execution times follows standard normal distribution.

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Acknowledgements

This work was supported by the National Research Foundation (NRF) Grants funded by Korean Government (2018R1A2B2005277).

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  1. School of Computing, Korea Advanced Institute of Science and Technology, Daejeon, Korea

    Myoungjun Lee & Soontae Kim

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Correspondence to Myoungjun Lee.

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Lee, M., Kim, S. Time-sensitivity-aware shared cache architecture for multi-core embedded systems. J Supercomput 75, 6746–6776 (2019). https://doi.org/10.1007/s11227-019-02891-w

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