Skip to main content
Log in

Design and reliability analysis of fault-tolerant shuffle exchange gamma logical neighborhood interconnection network

  • Published:
The Journal of Supercomputing Aims and scope Submit manuscript

Abstract

Multistage interconnection networks are used as a medium for interconnecting processors and memories in multiprocessor systems. Multistage interconnection networks are an effective substitute for crossbar switches, used in telephone network systems and parallel computers, due to their low cost, better performance and easy maintainability. In this paper, we propose new fault-tolerant hybrid multistage interconnection networks obtained from shuffle exchange gamma interconnection network (SEGIN) and logical neighborhood network named as shuffle exchange gamma logical neighborhood interconnection network (SEGLNIN). We evaluated the performance of SEGLNIN in terms of disjoint paths, reliability and hardware cost and compared it with some well-known MINs like shuffle exchange network (SEN), shuffle exchange network with one extra stage (SEN +) and shuffle exchange network with two extra stages (SEN + 2), SEGIN-1, and SEGIN-2. The results illustrate that the performance of the proposed SEGLNIN is better than that of the compared networks in terms of reliability and disjoint paths.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17

Similar content being viewed by others

References

  1. Pattavina A (1998) Switching theory: architectures and performance in broadband ATM Networks. Wiley, Chichester

    Google Scholar 

  2. Yunus NAM, Othman M (2015) Reliability evaluation for shuffle exchange interconnection network. Procedia Comput Sci 59:162–170

    Article  Google Scholar 

  3. Bistouni F, Jahanshahi M (2014) Analyzing the reliability of shuffle-exchange networks using reliability block diagrams. Reliab Eng Syst Saf 132:97–106

    Article  Google Scholar 

  4. Abd-El-Barr M (2007) Design and analysis of reliable and fault-tolerant computer systems. Imperial College Press, London

    MATH  Google Scholar 

  5. Lang T, Stone HS (1976) A Shuffle-exchange network with simplified control. IEEE Trans Comput C-25(1):55–65

    Article  MathSciNet  Google Scholar 

  6. Gunawan I (2008) Reliability analysis of shuffle-exchange network systems. Reliab Eng Syst Saf 93(2):271–276

    Article  Google Scholar 

  7. Bistouni F, Jahanshahi M (2015) Pars network: a multistage interconnection network with fault-tolerance capability. J Parallel Distrib Comput 75(2015):168–183

    Article  Google Scholar 

  8. Khanna G, Mishra R, Chaturvedi SK (2016) 4DGIN-3: a new design layout of 4-disjoint gamma interconnection network. J Parallel Distrib Comput 98:40–47

    Article  Google Scholar 

  9. Goyal NK, Rajkumar S (2017) Multi-source multi-terminal reliability evaluation of interconnection networks. Microsyst Technol 23(1):255–274

    Article  Google Scholar 

  10. Gunawan I (2008) Performance analysis of a multistage interconnection network system based on a minimum cut set method. Int J Perform Eng 4(2):111–120

    Google Scholar 

  11. Rajkumar S, Goyal NK (2016) Review of multistage interconnection networks reliability and fault-tolerance. IETE Tech Rev 33(3):223–230

    Article  Google Scholar 

  12. Khanna G, Mishra R, Chaturvedi SK (2017) Design of fault-tolerant shuffle exchange gamma interconnection network layouts. J Interconnect Netw 17(02):1750005

    Article  Google Scholar 

  13. IEC 1078 (1991) Analysis techniques for dependability-reliability block diagrams, 1st edn. Document Center, Inc., Belmont

    Google Scholar 

  14. Rajkumar S, Goyal NK (2014) Design of 4-disjoint gamma interconnection network layouts and reliability analysis of gamma interconnection networks. J Supercomput 69(1):468–491

    Article  Google Scholar 

Download references

Acknowledgements

Authors acknowledge the National Institute of Technology Jamshedpur, India, for providing the research opportunity and facilities.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Dilip Kumar Yadav.

Ethics declarations

Conflict of interest

The authors confirm that this article content has no conflicts of interest.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Prakash, A., Yadav, D.K. Design and reliability analysis of fault-tolerant shuffle exchange gamma logical neighborhood interconnection network. J Supercomput 75, 7934–7951 (2019). https://doi.org/10.1007/s11227-019-02929-z

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11227-019-02929-z

Keywords

Navigation