Skip to main content
SpringerLink
Log in

An enhanced cost-aware mapping algorithm based on improved shuffled frog leaping in network on chips

  • Published:
The Journal of Supercomputing Aims and scope Submit manuscript

Abstract

Network on chip (NoC) has been of great interest in recent years. However, according to the recent studies, high communication cost has been raised as the one most important challenges in mapping process in NoC. In order to address these issues, this research takes the advantages of the improved shuffled frog leaping based on two-dimensional torus networks in figure of an enhanced algorithm. In other words, using the proposed mapping category features, increase in the number of nodes has very little effect on the provided performance by the proposed algorithm, because it first improves the write cost of each cluster with less instead of high communication cost. Moreover, nodes having greater relevance in the graph of application are often adjacent to each other. Therefore, while the communication cost is reduced, the search space mapping gets larger which leads to easier and less costly access to the optimal mapping. In fact, between two nodes with higher weight, it is less distance to write in the network substrate. This reduction reduces the distance between the two nodes in the end, reducing the cost of communication. Simulation results show that the communication cost is improved by 3.62, 0.90, 0.72 and 1.35% compared to PSMAP algorithm for the 263dec mp3dec graph, Lmap algorithm for the 263enc mp3dec graph, Lmap algorithm for the MWD graph and PSMAP algorithm for MPEG-4 graph, respectively.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10

Similar content being viewed by others

Notes

  1. Simulated annealing with tabu search (SAT).

  2. Border mapping algorithm.

References

  1. Jiang S et al (2019) Testing aware dynamic mapping for path-centric network-on-chip test. Integration 67:134–143

    Article  Google Scholar 

  2. Tosun S, Ozturk O, Ozen M (2009) An ILP formulation for application mapping onto network-on-chips. In: 2009 International Conference on Application of Information and Communication Technologies. IEEE, pp 1–5

  3. Raghunathan V, Srivastava MB, Gupta RK (2003) A survey of techniques for energy efficient on-chip communication. In: Proceedings of the 40th Annual Design Automation Conference. ACM, pp 900–905

  4. Pande PP, Grecu C, Jones M, Ivanov A, Saleh R (2005) Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE Trans Comput 54(8):1025–1040

    Article  Google Scholar 

  5. Tinati M, Koohi S, Hessabi S (2019) Low-overhead thermally resilient optical network-on-chip architecture. Nano Commun Netw 20:31–47

    Article  Google Scholar 

  6. Janidarmian M, Khademzadeh A, Tavanpour M (2009) Onyx: a new heuristic bandwidth-constrained mapping of cores onto tile-based network on chip. IEICE Electron Express 6(1):1–7

    Article  Google Scholar 

  7. Upadhyay M, Shah M, Bhanu PV, Soumya J, Cenkeramaddi LR (2019) Multi-application based network-on-chip design for mesh-of-tree topology using global mapping and reconfigurable architecture. In: 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID). IEEE, pp 527–528

  8. Sahu PK, Chattopadhyay S (2013) A survey on application mapping strategies for network-on-chip design. J Syst Archit 59(1):60–76

    Article  Google Scholar 

  9. Kumar S et al (2002) A network on chip architecture and design methodology. In: Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002. IEEE, pp 117–124

  10. Mehran A, Saeidi S, Khademzadeh A, Afzali-Kusha A (2007) Spiral: a heuristic mapping algorithm for network on chip. IEICE Electron Express 4(15):478–484

    Article  Google Scholar 

  11. Kadri N, Koudil M (2019) A survey on fault-tolerant application mapping techniques for network-on-chip. J Syst Archit 92:39–52

    Article  Google Scholar 

  12. Reshadi M, Khademzadeh A, Reza A (2010) Elixir: a new bandwidth-constrained mapping for networks-on-chip. IEICE Electron Express 7(2):73–79

    Article  Google Scholar 

  13. Murali S, De Micheli G (2004) Bandwidth-constrained mapping of cores onto NoC architectures. In: Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004, vol 2. IEEE, pp 896–901

  14. Sahu PK, Venkatesh P, Gollapalli S, Chattopadhyay S (2011) Application mapping onto mesh structured network-on-chip using particle swarm optimization. In: 2011 IEEE Computer Society Annual Symposium on VLSI, 2011. IEEE, pp 335–336

  15. Sahu PK, Shah T, Manna K, Chattopadhyay S (2013) Application mapping onto mesh-based network-on-chip using discrete particle swarm optimization. IEEE Trans Very Large Scale Integr (VLSI) Syst 22(2):300–312

    Article  Google Scholar 

  16. Maqsood T, Ali S, Malik SU, Madani SA (2015) Dynamic task mapping for network-on-chip based systems. J Syst Archit 61(7):293–306

    Article  Google Scholar 

  17. Sahu PK, Manna K, Shah T, Chattopadhyay S (2015) A constructive heuristic for application mapping onto mesh based network-on-chip. J Circuits Syst Comput 24(08):1550126

    Article  Google Scholar 

  18. Alagarsamy A, Gopalakrishnan L (2016) SAT: a new application mapping method for power optimization in 2D—NoC. In: 2016 20th International Symposium on VLSI Design and Test (VDAT), 2016. IEEE, pp 1–6

  19. Xie Y, Liu Y (2017) A research on NoC mapping with quantum ant colony algorithm. In: 2017 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), 2017. IEEE, pp 874–877

  20. Taassori M, Niroomand S, Uysal S, Hadi-Vencheh A, Vizvari B (2016) Fuzzy-based mapping algorithms to design networks-on-chip. J Intell Fuzzy Syst 31(1):27–43

    Article  Google Scholar 

  21. Huang L et al (2018) A lifetime-aware mapping algorithm to extend MTTF of networks-on-chip. In: Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018. IEEE Press, pp 147–152

  22. Keley M, Khademzadeh A, Hosseinzadeh M, Center I (2019) Efficient mapping algorithm on mesh-based NoCs in terms of cellular learning automata. Int Arab J Inf Technol 16(2):312–322

    Google Scholar 

  23. Eusuff M, Lansey K, Pasha F (2006) Shuffled frog-leaping algorithm: a memetic meta-heuristic for discrete optimization. Eng Optim 38(2):129–154

    Article  MathSciNet  Google Scholar 

  24. Luo J, Chen M-R (2014) Improved shuffled frog leaping algorithm and its multi-phase model for multi-depot vehicle routing problem. Expert Syst Appl 41(5):2535–2545

    Article  Google Scholar 

  25. Yang B, Guang L, Xu TC, Säntti T, Plosila J (2010) Multi-application mapping algorithm for network-on-chip platforms. In: 2010 IEEE 26th Convention of Electrical and Electronics Engineers in Israel, 2010. IEEE, pp 000540–000544

Download references

Author information

Authors and Affiliations

  1. Faculty of Computer Engineering, Najafabad Branch, Islamic Azad University, Najafabad, Iran

    Bahador Boroumand, Elham Yaghoubi & Behrang Barekatain

  2. Big Data Research Center, Najafabad Branch, Islamic Azad University, Najafabad, Iran

    Elham Yaghoubi & Behrang Barekatain

Authors
  1. Bahador Boroumand
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Elham Yaghoubi
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Behrang Barekatain
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Elham Yaghoubi.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Boroumand, B., Yaghoubi, E. & Barekatain, B. An enhanced cost-aware mapping algorithm based on improved shuffled frog leaping in network on chips. J Supercomput 77, 498–522 (2021). https://doi.org/10.1007/s11227-020-03271-5

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11227-020-03271-5

Keywords

Search

Navigation