Skip to main content
SpringerLink
Log in

Dynamic scheduling of task graphs in multi-FPGA systems using critical path

  • Published:
The Journal of Supercomputing Aims and scope Submit manuscript

Abstract

SRAM-based FPGAs feature high performance and flexibility. Thus, they have found many applications in modern high-performance computing (HPC) systems. These systems suffer from the limitation of the computing resources problem for running HPC applications. Therefore, multi-FPGA systems have been emerged to alleviate such resource limitations. In this regard, efficient scheduling strategies are required to dynamically steer the execution of applications—represented as task graphs—on a set of connected FPGAs. In this paper, a heuristic-based dynamic critical path-aware scheduling technique named CPA is presented to schedule task graphs on multi-FPGA systems. The proposed technique, by considering the computation and communication capabilities of FPGAs, dynamically assigns priority to tasks in different steps in order to achieve better makespans. The proposed technique has been evaluated by conducting several experiments on real-world and three different shapes of random task graphs with different number of tasks, and its efficiency has been compared with that of three task graph scheduling approaches. The obtained results demonstrate that the proposed CPA technique outperforms well-known heuristic scheduling strategies and improves their makespan by 13.47% on average. In addition, the experiments show that the proposed technique generates the schedules in the order of milliseconds and the average of its yielded makespans is 12.05% longer than that of an optimum schedule.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6

Similar content being viewed by others

References

  1. Ghavidel A, Sedaghat Y, Naghibzadeh M (2019) Hybrid scheduling to enhance reliability of real-time tasks running on reconfigurable devices. J Supercomput. https://doi.org/10.1007/s11227-019-02976-6

    Article  Google Scholar 

  2. Shan J, Casu MR, Cortadella J, Lavagno L, Lazarescu MT (2019) Exact and heuristic allocation of multi-kernel applications to multi-FPGA platforms. In: Proceedings of the 56th Annual Design Automation Conference 2019. ACM, p 3

  3. Ramezani R, Clemente JA, Sedaghat Y, Mecha H (2016) Estimation of hardware task reliability on partially reconfigurable FPGAs. In: 16th European Conference on Radiation and Its Effects on Components and Systems (RADECS). IEEE, pp 1–4

  4. Njiki M, Elouardi A, Bouaziz S, Casula O, Roy O (2019) A multi-FPGA architecture-based real-time TFM ultrasound imaging. J Real Time Image Proc 16(2):505–521

    Article  Google Scholar 

  5. Sanaullah A, Yang C, Alexeev Y, Yoshii K, Herbordt MC (2018) Real-time data analysis for medical diagnosis using FPGA-accelerated neural networks. BMC Bioinform 19(18):490

    Article  Google Scholar 

  6. Mahmud N, El-Araby E (2018) Towards higher scalability of quantum hardware emulation using efficient resource scheduling. In: 2018 IEEE International Conference on Rebooting Computing (ICRC). IEEE, pp 1–10

  7. Lentaris G, Stratakos I, Stamoulias I, Soudris D, Lourakis M, Zabulis X (2019) High-performance vision-based navigation on SoC FPGA for spacecraft proximity operations. In: IEEE Transactions on Circuits and Systems for Video Technology

  8. Ramezani R (2020) A prefetch-aware scheduling for FPGA-based multi-task graph systems. J Supercomput. https://doi.org/10.1007/s11227-020-03153-w

    Article  Google Scholar 

  9. Clemente JA, Resano J, González C, Mozos D (2011) A hardware implementation of a run-time scheduler for reconfigurable systems. IEEE Trans Very Large Scale Integr VLSI Syst 19(7):1263–1276

    Article  Google Scholar 

  10. Owaida M, Alonso G (2018) Application partitioning on FPGA clusters: inference over decision tree ensembles. In: 2018 28th International Conference on Field Programmable Logic and Applications (FPL). IEEE, pp 295–2955

  11. Geng T et al (2018) FPDeep: acceleration and load balancing of CNN training on FPGA clusters. In: 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, pp 81–84

  12. Ramezani R, Sedaghat Y, Naghibzadeh M, Clemente JA (2017) Reliability and makespan optimization of hardware task graphs in partially reconfigurable platforms. IEEE Trans Aerosp Electron Syst 53(2):983–994

    Article  Google Scholar 

  13. Dai G, Huang T, Chi Y, Xu N, Wang Y, Yang H (2017) Foregraph: exploring large-scale graph processing on multi-fpga architecture. In: Proceedings of the 2017 ACM/SIGDA international symposium on field-programmable gate arrays. ACM, pp 217–226

  14. Farooq U, Mehrez H, Bhatti MK (2018) Inter-FPGA interconnect topologies exploration for multi-FPGA systems. Des Autom Embed Syst 22(1–2):117–140

    Article  Google Scholar 

  15. Kao C-C (2020) Resource and performance tradeoff for task scheduling of parallel reconfigurable architectures. J Circuits Syst Comput. https://doi.org/10.1142/S0218126620500292

    Article  Google Scholar 

  16. Jing C, Zhu Y, Li M (2013) Energy-efficient scheduling on multi-FPGA reconfigurable systems. Microprocess Microsyst 37(6–7):590–600

    Article  Google Scholar 

  17. Ramezani R, Sedaghat Y (2014) Scheduling periodic real-time hardware tasks on dynamic partial reconfigurable devices subject to fault tolerance. In: 4th International eConference on Computer and Knowledge Engineering (ICCKE). IEEE, pp 1–6

  18. Charitopoulos G, Koidis I, Papadimitriou K, Pnevmatikatos D (2017) Run-time management of systems with partially reconfigurable FPGAs. Integration 57:34–44

    Article  Google Scholar 

  19. Ramezani R, Sedaghat Y, Clemente JA (2017) Reliability improvement of hardware task graphs via configuration early fetch. IEEE Trans Very Large Scale Integr VLSI Syst 25(4):1408–1420

    Article  Google Scholar 

  20. Kao C-C (2015) Performance-oriented partitioning for task scheduling of parallel reconfigurable architectures. IEEE Trans Parallel Distrib Syst 26(3):858–867

    Article  Google Scholar 

  21. Liang H, Sinha S, Zhang W (2018) Parallelizing hardware tasks on multicontext FPGA with efficient placement and scheduling algorithms. IEEE Trans Comput Aided Des Integr Circuits Syst 37(2):350–363

    Article  Google Scholar 

  22. Koraei M, Jahre M, Fatemi SO (2017) DTP: enabling exhaustive exploration of FPGA temporal partitions for streaming HPC applications. In: Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. ACM, p 7

  23. Ramezani R, Sedaghat Y, Naghibzadeh M, Clemente JA (2018) A decomposition-based reliability and makespan optimization technique for hardware task graphs. Reliab Eng Syst Saf 180:13–24

    Article  Google Scholar 

  24. Wieczorek M, Prodan R, Fahringer T (2005) Scheduling of scientific workflows in the ASKALON grid environment. Acm Sigmod Record 34(3):56–62

    Article  Google Scholar 

  25. Etminani K, Naghibzadeh M (2007) A min–min max–min selective algorithm for grid task scheduling. In: 2007 3rd IEEE/IFIP International Conference in Central Asia on Internet. IEEE, pp 1–7

  26. Topcuoglu H, Hariri S, Wu M-Y (2002) Performance-effective and low-complexity task scheduling for heterogeneous computing. IEEE Trans Parallel Distrib Syst 13(3):260–274

    Article  Google Scholar 

  27. Yu T, Feng B, Stillwell M, Guo L, Ma Y, Thomson J (2018) Lattice-based scheduling for multi-FPGA systems. In: 2018 International Conference on Field-Programmable Technology (FPT). IEEE, pp 318–321

  28. Abdallah F, Tanougast C, Kacem I, Diou C, Singer D (2019) Genetic algorithms for scheduling in a CPU/FPGA architecture with heterogeneous communication delays. Comput Ind Eng 137:106006

    Article  Google Scholar 

  29. El Cadi AA, Souissi O, Atitallah RB, Belanger N, Artiba A (2018) Mathematical programming models for scheduling in a CPU/FPGA architecture with heterogeneous communication delays. J Intell Manuf 29(3):629–640

    Article  Google Scholar 

  30. Iturbe X (2013) Design and implementation of a reliable reconfigurable real-time operating system (R3TOS). PhD Thesis, University of Edinburgh

  31. Agne A et al (2014) ReconOS: an operating system approach for reconfigurable computing. Micro IEEE 34(1):60–71

    Article  Google Scholar 

  32. Al-Sharaeh S, Wells BE (1996) A comparison of heuristics for list schedules using the Box-method and P-method for random digraph generation. In: 28th Southeastern Symposium on System Theory. IEEE, pp 467–471

  33. XilinxCorporation (2012) Virtex-5 FPGA configuration user guide UG191 (v 3.11). www.xilinx.com/support/documentation/user_guides/ug191.pdf

  34. Singh V, Gupta I, Jana PK (2018) A novel cost-efficient approach for deadline-constrained workflow scheduling by dynamic provisioning of resources. Future Gener Comput Syst 79:95–110

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Software Engineering, Faculty of Computer Engineering, University of Isfahan, Isfahan, Iran

    Reza Ramezani

Authors
  1. Reza Ramezani
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Reza Ramezani.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Ramezani, R. Dynamic scheduling of task graphs in multi-FPGA systems using critical path. J Supercomput 77, 597–618 (2021). https://doi.org/10.1007/s11227-020-03281-3

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11227-020-03281-3

Keywords

Search

Navigation