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Design space exploration for an FPGA-based quantum annealing simulator with interaction-coefficient-generators

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Abstract

Quantum annealing simulation attracts much attention recently for solving combinatorial optimization problems. FPGA acceleration is a promising way to reduce the huge processing time in quantum annealing simulations. However, the performance of FPGA accelerators is often restricted by the small external memory bandwidth. To solve this problem, we propose a data-transfer-bottleneck-less FPGA-based accelerator for quantum annealing simulation. The proposed architecture is implemented on an FPGA and achieved up to 179 times speed-up compared to single-core CPU implementation. The proposed accelerator is two times faster compared to previous FPGA accelerators, and process up to 262,144 spins, which is not possible in any existing FPGA accelerators due to limited external memory capacity.

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Acknowledgements

This research is partly supported by MEXT KAKENHI, grant numbers 19K11998 and 20H04197.

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Authors and Affiliations

  1. Graduate School of Information Sciences, Tohoku University, 6-3-09, Aramaki-Aza-Aoba, Aoba, Sendai, Miyagi, 980-8579, Japan

    Chia-Yin Liu, Hasitha Muthumala Waidyasooriya & Masanori Hariyama

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  1. Chia-Yin Liu
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  2. Hasitha Muthumala Waidyasooriya
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  3. Masanori Hariyama
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Correspondence to Hasitha Muthumala Waidyasooriya.

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Liu, CY., Waidyasooriya, H.M. & Hariyama, M. Design space exploration for an FPGA-based quantum annealing simulator with interaction-coefficient-generators. J Supercomput 78, 1–17 (2022). https://doi.org/10.1007/s11227-021-03859-5

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