Skip to main content
SpringerLink
Log in

FT-PDC: an enhanced hybrid congestion-aware fault-tolerant routing technique based on path diversity for 3D NoC

  • Published:
The Journal of Supercomputing Aims and scope Submit manuscript

Abstract

In recent years, using three-dimensional Network-on-Chip (3D-NoC) has increased due to its high performance and integration of processing elements. However, as technology evolves, dimension of processing elements and the number of connections are decreasing and this increases their sensitivity to external factors. Therefore, fault detection is one of the most important challenges of designing 3D-NoC because even a transistor not working well may cause the whole system not to work. Many methods have been provided so far to make three-dimensional NoC tolerant against fault, but most of these methods suffer from some disadvantages. For example, their fault detection models are not strong enough or they do not consider the network traffic. Regarding these problems, in this article, a routing technique called fault-tolerant routing algorithm based on path diversity and congestion (FT-PDC) for three-dimensional mesh connectivity based on NoC is provided that has some features like finding the shortest current path, considering fault in vertical and horizontal links, and considering path diversity and congestion. In addition to these features, FT-PDC could solve the problems of other methods to a great extent considering network traffic conditions and sending the packet from a path in which traffic conditions are two hops better than the other paths. These features have led to the superiority of the proposed method over other methods. The simulation results in the Noxim simulator show that latency and throughput of FT-PDC compared to similar recent methods have significantly improved.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13

Similar content being viewed by others

References

  1. Venkataraman N, Kumar R (2019) Design and analysis of application specific network on chip for reliable custom topology. Comput Netw 158:69–76

    Article  Google Scholar 

  2. Ebrahimi M, Daneshtalab M, Liljeberg P, Plosila J, Flich J, Tenhunen H (2012) Path-based partitioning methods for 3D networks-on-chip with minimal adaptive routing. IEEE Trans Comput 63(3):718–733

    MathSciNet  MATH  Google Scholar 

  3. Ronak S (2018) Design and evaluation of high-performance and fault-tolerant routing algorithms for 3D-NoCs. UC Irvine Electronic Theses and Dissertations. doi: ProQuest ID: Salamat_uci_0030D_15171. Merritt ID: ark:/13030/m5p03551. Retrieved from https://escholarship.org/uc/item/7kz2n9cn.

  4. Ahmed AB (2015) High-throughput architecture and routing algorithms towards the design of reliable mesh-based many-core network-on-chip systems. Ph. D. Thesis, Graduate School of Computer Science and Engineering

  5. Wang X, Jiang Y, Yang M, Li H, Mak T (2017) HRC: a 3D NoC architecture with genuine support for runtime thermal-aware task management. IEEE Trans Comput 66(10):1676–1688

    Article  MathSciNet  Google Scholar 

  6. Karthikeyan A, Kumar PS (2018) GALS implementation of randomly prioritized buffer-less routing architecture for 3D NoC. Clust Comput 21(1):177–187

    Article  Google Scholar 

  7. Mohseni Z, Reshadi M (2018) A deadlock-free routing algorithm for irregular 3D network-on-chips with wireless links. J Supercomput 74(2):953–969

    Article  Google Scholar 

  8. Salamat R (2018) Design and evaluation of high-performance and fault-tolerant routing algorithms for 3D-NoCs. UC Irvine Electronic Theses and Dissertations. 2018, Electrical and Computer Engineering Faculty, University of California, Irvine

  9. Ahmed AB, Abdallah AB (2016) Adaptive fault-tolerant architecture and routing algorithm for reliable many-core 3D-NoC systems. J Parallel Distrib Comput 93:30–43

    Article  Google Scholar 

  10. Tagel M. System-level Design of Timing-sensitive Network-on-chip Based Dependable Systems. TUT Press; 2012.

  11. Akbari S, Shafiee A, Fathy M, Berangi R (2012) AFRA: A low cost high performance reliable routing for 3D mesh NoCs. In: Proceedings of the Conference on Design, Automation and Test in Europe: EDA Consortium p. 332–7

  12. Mogharrabi-Rad Z, Yaghoubi E (2019) ADFT: an adaptive, distributed, fault-tolerant routing algorithm for 3D mesh-based networks-on-chip. Int J Internet Technol Secur Trans 10(4):481–490

    Google Scholar 

  13. Zhou J, Li H, Wang T, Li X (2016) LOFT: a low-overhead faul4t-tolerant routing scheme for 3D NoCs. Integr VLSI J52(2):41–50

    Article  Google Scholar 

  14. Ebrahimi M, Daneshtalab M, Plosila J (2013) Fault-tolerant routing algorithm for 3D NoC using hamiltonian path strategy. In: 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE). p. 1601–4

  15. Zhou J, Li H, Fang Y, Wang T, Cheng Y, Li X (2014) HARS: A high-performance reliable routing scheme for 3D NoCs. In: 2014 IEEE Computer Society Annual Symposium on VLSI. p. 392–7

  16. Naghibi Jouybari H, Mohammadi K (2014) A low overhead, fault tolerant and congestion aware routing algorithm for 3D mesh-based network-on-chips. Microprocess Microsyst 38(8):991–999

    Article  Google Scholar 

  17. Dai J, Li R, Jiang X, Watanabe T (2018) PDA-HyPAR: Path-diversity-aware hybrid planar adaptive routing algorithm for 3D NoCs. In: Proc 19th International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA,. 131–7.

  18. Sun M, Liu Q, Yan B, Wang X (2018) Minimally buffered router and deflection routing algorithm for 3D Mesh NoC. In: Proc Recent Developments in Intelligent Computing, Communication and Devices, Springer, Singapore. 515–22.

  19. Vahdatpanah F, Elahi M, Kashi S, Taheri E, Patooghy A (2019) 3DEP: a efficient routing algorithm to evenly distribute traffic over 3D Network-on-Chips. In: 2019 27th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP): IEEE 237–41

  20. Kunthara RG, James RK, Sleeba SZ, Jose J (2021) Traffic aware routing in 3D NoC using interleaved asymmetric edge routers. Nano Commun Netw 27:100334. https://doi.org/10.1016/j.nancom.2020.100334

    Article  Google Scholar 

  21. Boroumand B, Yaghoubi E, Barekatain B (2021) An enhanced cost-aware mapping algorithm based on improved shuffled frog leaping in network on chips. J Supercomput 77(1):498–522. https://doi.org/10.1007/s11227-020-03271-5

    Article  Google Scholar 

  22. Mazaheri Kalahroudi P, Yaghoubi E, Barekatain B (2021) IAM: an improved mapping on a 2-D network on chip to reduce communication cost and energy consumption. Photon Netw Commun 41(1):78–92. https://doi.org/10.1007/s11107-020-00911-x

    Article  Google Scholar 

  23. Akbar R, Etedalpour A, Safaei F (2016) An efficient fault-tolerant routing algorithm in NoCs to tolerate permanent faults. J Supercomput 72(12):4629–4650

    Article  Google Scholar 

  24. Chen Y, Chang E, Hsin H, Chen K, Wu A (2017) Path-diversity-aware fault-tolerant routing algorithm for network-on-chip systems. IEEE Trans Parallel Distrib Syst 28(3):838–849

    Article  Google Scholar 

  25. Ahmed A, Abdallah A (2012) LA-XYZ: low latency, high throughput look-ahead routing algorithm for 3D network-on-chip (3D-NoC). In: Proc IEEE 6th International Symposium on Embedded Multicore SoCs, Aizu-Wakamatsu, Fukushima, Japan. 167–74

  26. Ahmed A, Abdallah A (2014) Graceful deadlock-free fault-tolerant routing algorithm for 3D network-on-chip architectures. J Parallel Distrib Comput 74(4):2229–2240

    Article  Google Scholar 

  27. Rodrigo S, Medardoni S, Flich J, Bertozzi D, Duato J (2009) Efficient implementation of distributed routing algorithm for NoCs. IET Comput Digital Tech 3(5):460–475

    Article  Google Scholar 

  28. Noxim. The NoC simulator developed by the University of Catania, Italy.

  29. Martin MMK, Sorin DJ, Beckmann BM, Marty MR, Xu M, Alameldeen AR et al (2005) Multifacet’s general execution-driven multiprocessor simulator (GEMS) toolset. SIGARCH Comput Archit News 33(4):92–99. https://doi.org/10.1145/1105734.1105747

    Article  Google Scholar 

  30. Magnusson PS, Christensson M, Eskilson J, Forsgren D, Hallberg G, Hogberg J et al (2002) Simics: a full system simulation platform. Computer 35(2):50–58. https://doi.org/10.1109/2.982916

    Article  Google Scholar 

  31. Bienia C, Kumar S, Singh JP, Li K (2008) The PARSEC benchmark suite: characterization and architectural implications. In: Proceedings of the 17th international conference on Parallel architectures and compilation techniques. Toronto, Ontario, Canada: Association for Computing Machinery p. 72–81

Download references

Author information

Authors and Affiliations

  1. Faculty of Computer Engineering, Najafabad Branch, Islamic Azad University, Najafabad, Iran

    Elham Khodadadi, Behrang Barekatain, Elham Yaghoubi & Zahra Mogharrabi-Rad

  2. Big Data Research Center, Najafabad Branch, Islamic Azad University, Najafabad, Iran

    Behrang Barekatain & Elham Yaghoubi

Authors
  1. Elham Khodadadi
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Behrang Barekatain
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Elham Yaghoubi
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Zahra Mogharrabi-Rad
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Behrang Barekatain.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Khodadadi, E., Barekatain, B., Yaghoubi, E. et al. FT-PDC: an enhanced hybrid congestion-aware fault-tolerant routing technique based on path diversity for 3D NoC. J Supercomput 78, 523–558 (2022). https://doi.org/10.1007/s11227-021-03906-1

Download citation

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11227-021-03906-1

Keywords

Search

Navigation