Skip to main content
Log in

A new approach for design of an efficient FPGA-based reconfigurable convolver for image processing

  • Published:
The Journal of Supercomputing Aims and scope Submit manuscript

Abstract

Two-dimensional convolution plays a fundamental role in different image processing applications. Image convolving with different kernel sizes enriches the overall performance of image processing applications. In this regard, it is necessary to design of reconfigurable convolver with respect to desired kernel sizes list. In this paper, a novel approach is presented for implementation of an area-efficient reconfigurable convolver with appropriate throughput and convolution computational time for an arbitrary kernel size list. This approach is based on the adjustment of logical blocks arrangement in the conventional convolvers. The feasibility and benefits of the proposed approach are demonstrated through a case study of the design implementation on an FPGA platform using the XILINX ISE software. Compared to the well-known reconfigurable convolvers, the proposed design significantly reduces convolution computational time and improves throughput with a reasonable number of hardware resources. For instance, the proposed reconfigurable convolver only requires 0.38 ms to perform a 3 × 3 convolution on a 268 × 460 image with 8-bit pixels and only occupies 455 slices resource of Xilinx Virtex-4 (XC4VLX25) FPGA, in which the throughput of 324 million outputs per second (MOPS) is provided with 81 MHz clock frequency for kernel size of 3 × 3. On average, the MPOS of the proposed approach is approximately improved by 43.13% in relation to the other considered alternatives. Experimental results confirm that the proposed reconfigurable convolver is a very competitive design among the alternative reconfigurable convolvers.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9

Similar content being viewed by others

References

  1. Lee J, Tang H, Park J (2018) Energy efficient canny edge detector for advanced mobile vision applications. IEEE Trans Circuits Syst Video Technol 28(4):1037–1046. https://doi.org/10.1109/TCSVT.2016.2640038

    Article  Google Scholar 

  2. Sunwoo MH, Oh SK (2004) A multiplierless 2-D convolver chip for real-time image processing. J VLSI Signal Process Syst Signal Image Video Technol 38(1):63–71. https://doi.org/10.1023/B:VLSI.0000028534.35761.a8

    Article  Google Scholar 

  3. Kalbasi M, Nikmehr H (2019) A fine-grained pipelined 2-D convolver for high-performance applications. IEEE Trans Circuits Syst II Express Briefs 66(1):146–150. https://doi.org/10.1109/TCSII.2018.2832064

    Article  Google Scholar 

  4. Özyurt F (2020) Efficient deep feature selection for remote sensing image recognition with fused deep learning architectures. J Supercomput 76(11):8413–8431. https://doi.org/10.1007/s11227-019-03106-y

    Article  Google Scholar 

  5. Lei F, Liu X, Dai Q, Ling BW-K (2020) Shallow convolutional neural network for image classification. SN Appl Sci 2(1):1–8. https://doi.org/10.1007/s42452-019-1903-4

    Article  Google Scholar 

  6. Perri S, Lanuzza M, Corsonello P, Cocorullo G (2005) A high-performance fully reconfigurable FPGA-based 2D convolution processor. Microprocess Microsyst 29(8–9):381–391. https://doi.org/10.1016/j.micpro.2004.10.004

    Article  Google Scholar 

  7. Fons F, Fons M, Cantó E (2011) Run-time self-reconfigurable 2D convolver for adaptive image processing. Microelectronics J 42(1):204–217. https://doi.org/10.1016/j.mejo.2010.08.008

    Article  Google Scholar 

  8. Du L et al (2018) A reconfigurable streaming deep convolutional neural network accelerator for internet of things. IEEE Trans Circuits Syst I Regul Pap 65(1):198–208. https://doi.org/10.1109/TCSI.2017.2735490

    Article  Google Scholar 

  9. Fons F, Fons M, Cantó E, López M (2013) Real-time embedded systems powered by FPGA dynamic partial self-reconfiguration: a case study oriented to biometric recognition applications. J Real-Time Image Process 8(3):229–251. https://doi.org/10.1007/s11554-010-0186-1

    Article  Google Scholar 

  10. Ozturk S, Ozkaya U, Akdemir B, Seyfi L (2018) Convolution kernel size effect on convolutional neural network in histopathological image processing applications. In: 2018 International Symposium on Fundamentals of Electrical Engineering, ISFEE. https://doi.org/10.1109/ISFEE.2018.8742484

  11. Phu HV, Minh Tan T, Van Men P, Van Hieu N, Van Cuong T (2019) Design and implementation of configurable convolutional neural network on FPGA. In: Proceedings—2019 6th NAFOSTED Conference on Information and Computer Science, NICS 2019, pp 298–302. https://doi.org/10.1109/NICS48868.2019.9023810

  12. Di Carlo S, Gambardella G, Marco M, Rolfo D, Tiotto G, Prinetto P (2011) An area-efficient 2-D convolution implementation on FPGA for space applications. In: International Design and Test Workshop, pp 88–92. https://doi.org/10.1109/IDT.2011.6123108

  13. Licciardo GD, Cappetta C, Di Benedetto L (2017) FPGA optimization of convolution-based 2D filtering processor for image processing. In: 2016 8th Computer Science and Electronic Engineering Conference, CEEC 2016—Conference Proceedings, pp 180–185. https://doi.org/10.1109/CEEC.2016.7835910

  14. Zhang H, Xia M, Hu G (2007) A multiwindow partial buffering scheme for FPGA-based 2-D convolvers. IEEE Trans Circuits Syst II Express Briefs 54(2):200–204. https://doi.org/10.1109/TCSII.2006.886898

    Article  Google Scholar 

  15. Salvador R, Otero A, Mora J, De La Torre E, Riesgo T, Sekanina L (2013) Self-reconfigurable evolvable hardware system for adaptive image processing. IEEE Trans Comput 62(8):1481–1493. https://doi.org/10.1109/TC.2013.78

    Article  MathSciNet  MATH  Google Scholar 

  16. Sreenivasulu M, Meenpal T (2019) Efficient hardware implementation of 2D convolution on FPGA for image processing application. In: 2019 IEEE International Conference on Electrical, Computer and Communication Technologies (ICECCT), pp 1–5. https://doi.org/10.1109/ICECCT.2019.8869347

  17. BinMa Z, Yang Y, Liu YX, Bharath AA (2016) Recurrently decomposable 2-D convolvers for FPGA-based digital image processing. IEEE Trans Circuits Syst II Express Briefs 63(10):979–983. https://doi.org/10.1109/TCSII.2016.2536202

    Article  Google Scholar 

  18. Strollo AGM, Napoli E, De Caro D, Saggese GP (2001) A reconfigurable 2D convolver for real-time SAR imaging. Proc IEEE Int Conf Electron Circuits Syst 2:741–744. https://doi.org/10.1109/ICECS.2001.957581

    Article  Google Scholar 

  19. Perri S, Corsonello P (2007) VLSI implementations of efficient isotropic flexible 2D convolvers. IET Circuits Devices Syst 1(4):263–269. https://doi.org/10.1049/iet-cds:20070056

    Article  Google Scholar 

  20. Bosi B, Bois G, Savaria Y (1999) Reconfigurable pipelined 2-D convolvers for fast digital signal processing. IEEE Trans Very Large Scale Integr Syst 7(3):299–308. https://doi.org/10.1109/92.784091

    Article  Google Scholar 

  21. Sriram V, Kearney D (2007) A FPGA implementation of variable kernel convolution. In: Eighth International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2007), pp 105–110. https://doi.org/10.1109/PDCAT.2007.45

  22. Wang W, Sun G (2019) A DSP48-based reconfigurable 2-D convolver on FPGA. In: Proceedings—2019 International Conference on Virtual Reality and Intelligent Systems, ICVRIS 2019, pp 342–345. https://doi.org/10.1109/ICVRIS.2019.00089

  23. Cabello F, León J, Iano Y, Arthur R (2015) Implementation of a fixed-point 2D Gaussian filter for image processing based on FPGA. In: 2015 Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA), Poznan, pp 28–33. https://doi.org/10.1109/SPA.2015.7365108

  24. Kalbasi M, Nikmehr H (2020) Noise-robust, reconfigurable canny edge detection and its hardware realization. IEEE Access 8:39934–39945. https://doi.org/10.1109/ACCESS.2020.2976860

    Article  Google Scholar 

  25. Zou G, Fu G, Gao M, Shen J, Yin L, Ben X (2019) A novel construction method of convolutional neural network model based on data-driven. Multimed Tools Appl 78(6):6969–6987. https://doi.org/10.1007/s11042-018-6449-8

    Article  Google Scholar 

  26. Liu B, Yao K, Huang M, Zhang J, Li Y, Li R (2018) Gastric pathology image recognition based on deep residual networks. Proc Int Comput Softw Appl Conf 2:408–412. https://doi.org/10.1109/COMPSAC.2018.10267

    Article  Google Scholar 

  27. Virtex-4 FPGAs Data Sheet (2010) Xilinx, Inc. https://www.xilinx.com/support/documentation/data_sheets/ds112.pdf

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Abbas Dehghani.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Dehghani, A., Kavari, A., Kalbasi, M. et al. A new approach for design of an efficient FPGA-based reconfigurable convolver for image processing. J Supercomput 78, 2597–2615 (2022). https://doi.org/10.1007/s11227-021-03963-6

Download citation

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11227-021-03963-6

Keywords

Navigation