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RTFTL: design and implementation of real-time FTL algorithm for flash memory

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Abstract

The optimization of traditional FTL(Flash Translation Layer) algorithm is mainly aimed at the average response time of flash memory read and write operation on a flash chip, because of the Out-of-place update, traditional FTL algorithm writes data in a new free page each time, and a new block is assigned when a block is full. Therefore, when the flash memory is almost full, a written request will lead to a garbage collection, in which there will be many write copies, which will lead to a significant decrease in response time. In this paper, we optimize the traditional FTL algorithm and propose an FTL algorithm that guarantees real-time performance by shortening the worst response time of the request as a measure of the guaranteed flash Qos (Quality of Service) under the condition that the address mapping is provided the upper layer. The algorithm adopts the idea of space-for-time and spreads the written copy of flash memory to each write request so that the worst response time of the write request is significantly reduced. The algorithm also wears balancing considerations to the algorithm. After experimental verification, the proposed algorithm has advantages over existing FTL algorithms in terms of real-time performance and has a performance improvement of more than 11% in terms of average response time and wear balance. By the way, we add the wear-level module into an algorithm. According to improving the algorithm, the worst response time has shorten 47.6%.

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The data set used in this article is an open source. Data source address: https://www.github.com/.

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Acknowledgements

We are very grateful to Dr. Zhang Fan and Mr Chen Chen for providing us with RTFTL Prototype and many instructive comments. This work is supported by the National Natural Science Foundation of China (61872284); Industrial field of general projects of science and Technology Department of Shaanxi Province(2020GY-012); Industrialization Project of Shaanxi Provincial Department of Education (21JC017); "Thirteenth Five-Year" National Key R&D Program Project (Project Number: 2019YFD1100901); Yulin Science and Technology Project(2019-175); Natural Science Foundation of Shannxi Province, China(2014JM2-6127); The project sponsored by the scientific research Foundation for the returned overseas Chinese scholars, SEM No.[2014] 1685.

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Authors and Affiliations

  1. School of Information and Control Engineering, Xi’an University of Architecture and Technology, Xi’an, 710054, China

    Qinlu He, Genqing Bian & Weiqi Zhang

  2. Shaan Xi Institute of Metrology Science, Xi’an, 710043, China

    Zhen Li

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  1. Qinlu He
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He, Q., Bian, G., Zhang, W. et al. RTFTL: design and implementation of real-time FTL algorithm for flash memory. J Supercomput 78, 18959–18993 (2022). https://doi.org/10.1007/s11227-022-04602-4

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