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Hardware implementation of fault tolerance NoC core mapping

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Abstract

Due to performance and reliability, network on chip (NoC) is considered to be the future generation interconnect technique for multiple cores in a chip. This paper proposes a system level core mapping technique which improves the performance of the whole system, while rectifying the temporary faults and permanent faults in the system using error correcting codes and spare core. This technique mainly focuses on the core mapping and faults on the system. This results in reliable core mapping and improved performance when a fault-related error occurs on an NoC. At last, the proposed core mapping technique is simulated and verified on FPGA board (Kintex-7 FPGA KC705 Evaluation Kit).

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Acknowledgements

This publication is an outcome of the R&D work undertaken in the project under Visvesvaraya Ph.D. scheme, Department of Electronics and Information Technology, Ministry of Communication and IT, Government of India and Media Lab Asia.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, National Institute of Technology, Farmagudi, Goa, India

    Naresh Kumar Reddy Beechu, Vasantha Moodabettu Harishchandra & Nithin Kumar Yernad Balachandra

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  1. Naresh Kumar Reddy Beechu
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  2. Vasantha Moodabettu Harishchandra
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  3. Nithin Kumar Yernad Balachandra
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Correspondence to Naresh Kumar Reddy Beechu.

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Beechu, N.K.R., Moodabettu Harishchandra, V. & Yernad Balachandra, N. Hardware implementation of fault tolerance NoC core mapping. Telecommun Syst 68, 621–630 (2018). https://doi.org/10.1007/s11235-017-0412-2

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