Abstract
Memory resources are a serious bottleneck in many real-time multicore systems. Previous work has shown that, in the worst case, execution time of memory intensive tasks can grow linearly with the number of cores in the system. To improve hard real-time utilization, a real-time multicore system should be scheduled according to a memory-centric scheduling approach if its workload is dominated by memory intensive tasks. In this work, a memory-centric scheduling technique is proposed where (a) core isolation is provided through a coarse-grained (high-level) Time Division Multiple Access (TDMA) memory schedule; and (b) the scheduling policy of each core “promotes” the priority of its memory intensive computations above CPU-only computation when memory access is permitted by the high-level schedule. Our evaluation reveals that under high memory demand, our scheduling approach can improve hard real-time task utilization significantly compared to traditional multicore scheduling.
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Notes
However, note that the figure does not represent the worst-case contribution of lower priority jobs to \(\mathcal{M}_{4}\), since there could be increased blocking by either J 5 or another lower priority job with a longer memory phase.
References
Aeronautical Radio Inc. ARINC 653 specification. http://www.arinc.com/
Akesson B, Goossens K, Ringhofer M (2007) Predator: a predictable sdram memory controller. In: Proceedings of the 5th IEEE/ACM international conference on hardware/software codesign and system synthesis, CODES+ISSS’07, pp 251–256
Alvarez M, Salami E, Ramirez A, Valero M (2005) A performance characterization of high definition digital video decoding using h. 264/avc. In: Proc. of the IEEE international workload characterization symposium, Oct 2005
Anderson JH, Calandrino JM, Devi UMC (2006) Real-time scheduling on multicore platforms. In: Proceedings of the 12th IEEE real-time and embedded technology and applications symposium, pp 179–190
Andersson B, Easwaran A, Lee J (2010) Finding an upper bound on the increase in execution time due to contention on the memory bus in cots-based multicore systems. ACM Sigbed Rev 7(1)
Audsley NC, Burns A, Richardson M, Tindell K, Wellings A (1993) Applying new scheduling theory to static priority preemptive scheduling. Softw Eng J 8(8):284–292
Bui BD, Caccamo M, Sha L, Martinez J (2008) Design and evaluation of a cache partitioned environment for real-time embedded systems. In: Proceedings of the 14th IEEE international conference on embedded and real-time computing systems and applications (RTCSA), KaoHsiung, Taiwan
Buttazzo G (1997) Hard real-time computing systems: predictable scheduling algorithms and applications. Kluwer Academic, Boston
Calandrino JM, Anderson JH (2009) On the design and implementation of a cache-aware multicore real-time scheduler. In: 2009 21st Euromicro conference on real-time systems. IEEE, New York, pp 194–204
Chattopadhyay S, Roychoudhury A, Mitra T (2010) Modeling shared cache and bus in multi-cores for timing analysis. In: Proceedings of the 13th international workshop on software & compilers for embedded systems. ACM, New York, pp 1–10
Davis RI, Burns A (2010, to appear) A survey of hard real-time scheduling for multiprocessor systems. ACM Comput Surv
Edwards SA, Lee EA (2007) The case for the precision timed (PRET) machine. In: DAC’07: proceedings of the 44th annual design automation conference
Freescale P4080 website (2012). http://www.freescale.com
Guan N, Stigge M, Yi W, Yu G (2009) Cache-aware scheduling and analysis for multicores. In: Proceedings of the seventh ACM international conference on embedded software
Holman P, Anderson JH (2005) Adapting Pfair scheduling for symmetric multiprocessors. J Embed Comput 1(4):543–564
Jain R, Hughes CJ, Adve SV (2002) Soft real-time scheduling on simultaneous multithreading processors. In: Proceedings of the real-time systems symposium
Jayachandran P, Abdelzaher T (2008) Transforming distributed acyclic systems into equivalent uniprocessors under preemptive and non-preemptive scheduling. In: Proceedings of the 20th Euromicro conference on real-time systems, Prague, Czech Republic, July 2008
Jayachandran P, Abdelzaher T (2010) Reduction-based schedulability analysis of distributed systems with cycles in the task graph. Real-Time Syst 46(1):121–151
Kato S, Yamasaki N (2006) Extended U-link scheduling to increase the execution efficiency for SMT real-time systems. In: Proceedings of the 12th IEEE international conference on embedded and real-time computing systems and applications, pp 373–377
Kato S, Ishikawa Y, (Raj) Rajkumar R (2011) Cpu scheduling and memory management for interactive real-time applications. Real-Time Syst 47
Kenna CJ, Herman JL, Brandenburg BB, Mills AF, Anderson JH (2011) Soft real-time on multiprocessors: are analysis-based schedulers really worth it? In: Real-time systems symposium (RTSS), 2011 IEEE 32nd, Dec 2011
Lattner C, Adve V (2004) LLVM: a compilation framework for lifelong program analysis and transformation. In: Proc. of the international symposium of code generation and optimization, San Jose, CA, USA, Mar 2004
Li Y, Suhendra V, Liang Y, Mitra T, Roychoudhury A (2009) Timing analysis of concurrent programs running on shared cache multi-cores. In: 30th IEEE real-time systems symposium. IEEE, New York, pp 57–67
Liu CL, Layland JW (1973) Scheduling algorithms for multiprogramming in a hard-real-time environment. J Assoc Comput Mach 20(1)
Paolieri M, Quinones E, Cazorla FJ, Valero M (2009) An analyzable memory controller for hard real-time CMPs. IEEE Embedded Syst Lett 1(4)
Paolieri M, Quinones E, Cazorla FJ, Bernat G, Valero M (2009) Hardware support for wcet analysis of hard real-time multicore systems. In: Proceedings of the international symposium on computer architecture (ISCA)
Pellizzoni R, Betti E, Bak S, Yao G, Criswell J, Caccamo M, Kegley R (2011) A predictable execution model for cots-based embedded system. In: Proceedings of the 17th IEEE real-time and embedded technology and applications symposium, Chicago, IL, USA, April 2011
Pellizzoni R, Schranzhofer A, Chen J-J, Caccamo M, Thiele L (2010) Worst case delay analysis for memory interference in multicore systems. In: Proceedings of design, automation and test in Europe (DATE), Dresden, Germany, Mar 2010
Pellizzoni R, Bui BD, Caccamo M, Sha L (2008) Coscheduling of CPU and I/O transactions in COTS-based embedded systems. In: Proceedings of the 2008 real-time systems symposium, Washington, DC, USA. IEEE Computer Society, Los Alamitos, pp 221–231
Pike J (2009) Hh-60g pave hawk. www.globalsecurity.org/military/systems/aircraft/hh-60g.htm
Poovey JA, Conte TM, Levy M, Gal-On S (2009) A benchmark characterization of the eembc benchmark suite. IEEE MICRO 29(5):18–29
Reineke J, Grund D, Berg C, Wilhelm R (2007) Timing predictability of cache replacement policies. Real-Time Syst 37(2)
Rosen J, Eles P, Andrei A, Peng Z (2007) Bus access optimization for predictable implementation of real-time applications on multiprocessor systems-on-chip. In: Proceedings of the 28th IEEE real-time system symposium, December 2007
Schliecker S, Negrean M, Ernst R (2010) Bounding the shared resource load for the performance analysis of multiprocessor systems. In: Proceedings of the conference on design, automation and test in Europe, pp 759–764
Schranzhofer A, Chen JJ, Thiele L (2010) Timing analysis for TDMA arbitration in resource sharing systems. In: 16th IEEE real-time and embedded technology and applications symposium, pp 215–224
Whitham J, Audsley N (2009) Implementing time-predictable load and store operations. In: Proc. of the intl. conf. on embedded systems (EMSOFT), Grenoble, France, Oct 2009
Yang T, Liu T, Berger ED, Kaplan SF, Moss JEB (2008) Redline: first class support for interactivity in commodity operating systems. In: Proceedings of the 8th USENIX conference on operating systems design and implementation, OSDI’08, pp 73–86
Acknowledgements
The authors would like to thank Lui Sha for his insightful suggestions. The material presented in this paper is based upon work supported by Lockheed Martin, NSERC and NSF under Award No. CNS-1035736. Any opinions, findings, and conclusions or recommendations expressed in this publication are those of the authors and do not necessarily reflect the views of the Lockheed Martin, NSERC or NSF.
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Yao, G., Pellizzoni, R., Bak, S. et al. Memory-centric scheduling for multicore hard real-time systems. Real-Time Syst 48, 681–715 (2012). https://doi.org/10.1007/s11241-012-9158-9
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DOI: https://doi.org/10.1007/s11241-012-9158-9