Mixed-criticality scheduling on cluster-based manycores with shared communication and storage resources

Abstract

The embedded system industry is facing an increasing pressure for migrating from single-core to multi- and many-core platforms for size, performance and cost purposes. Real-time embedded system design follows this trend by integrating multiple applications with different safety criticality levels into a common platform. Scheduling mixed-criticality applications on today’s multi/many-core platforms and providing safe worst-case response time bounds for the real-time applications is challenging given the shared platform resources. For instance, sharing of memory buses introduces delays due to contention, which are non-negligible. Bounding these delays is not trivial, as one needs to model all possible interference scenarios. In this work, we introduce a combined analysis of computing, memory and communication scheduling in a mixed-criticality setting. In particular, we propose: (1) a mixed-criticality scheduling policy for cluster-based many-core systems with two shared resource classes, i.e., a shared multi-bank memory within each cluster, and a network-on-chip for inter-cluster communication and access to external memories; (2) a response time analysis for the proposed scheduling policy, which takes into account the interferences from the two classes of shared resources; and (3) a design exploration framework and algorithms for optimizing the resource utilizations under mixed-criticality timing constraints. The considered cluster-based architecture model describes closely state-of-the-art many-core platforms, such as the Kalray MPPA^®-256. The applicability of the approach is demonstrated with a real-world avionics application. Also, the scheduling policy is compared against state-of-the-art scheduling policies based on extensive simulations with synthetic task sets.

Notation summary

Notation	Meaning	Source
System model—Sect. 3
$\tau$	Task set	Fixed
$L$	Number of criticality levels	Fixed
$W_i$, $\chi _i$	Period and criticality level of task $\tau _i$	Fixed
$C_i(\ell )$	Execution profile with lower and upper bounds on execution time	Fixed
	($e_i$) and number of memory accesses ($\mu _i$) of $\tau _i$ at level $\ell \le \chi _i$	Fixed
$C_{i,deg}$	Execution profile of $\tau _i$ at level of assurance $\ell > \chi _i$	Fixed
$\mathcal {D} ep$	Dependency graph	The edges (dependencies) are known,
		but their weight (minimum distance constraint)
		is determined from NoC analysis (Sect. 5.2)
$\mathcal {P}$	Set of processing cores on a target cluster	Fixed
$T_{acc}$	Memory access latency	Fixed
$\mathcal {M}_{\tau }$	Mapping of tasks of $\tau$ to cores of $\mathcal {P}$	Optimized in Sect. 6
Remote fetch protocol—Sect. 3.2
$\tau _{init,i} \rightarrow \tau _i$	Initiating task for remote data fetch, task using fetched data	Fixed
WCNT	Worst-case time for transfer of notification from $\tau _{init,i}$	Computed in Sect. 5.2 (Eq. 12)
	to listener in remote cluster
WCRST	Worst-case time for set-up of DMA transfer in remote cluster	Based on measurements
WCDFT	Worst-case time for complete transfer of data from remote cluster	Computed in Sect. 5.2 (Eq. 12)
Flexible time-triggered and synchronization based scheduling—Sect. 4
$h$	FTTS cycle	Computed as hyper-period of $\tau$
$\mathcal {F}$	Set of FTTS frames	Computed after selecting frame lengths
$\mathcal {L}_f$	Length of FTTS frame $f$	Selected manually
$barriers(f,l)_k$	Worst-case length of $k$-th sub-frame in frame $f$ at level $\ell$	Computed for a given $\mathcal {M}_{\tau }, \mathcal {M}_{mem}$ in Sect. 5.1 (Eq. 6)
Response time analysis—Sect. 5
$\mathcal {I}$	Memory interference graph	Consisting of $\mathcal {E}_1, \mathcal {E}_2$
$\mathcal {E}_1$	Mapping of tasks to memory blocks	Fixed
$\mathcal {E}_2$	Mapping of memory blocks to memory banks	Optimized in Sect. 6
$\mathcal {M}_{mem}$	Equivalent to $\mathcal {E}_2$	Optimized in Sect. 6
$D$	Mutual delay matrix	Computed in Sect. 5.1.1 and 5.1.2
Rx	Special node in $\mathcal {I}$ indicating a high-priority NoC Rx access	Added to $\mathcal {I}$ in Sect. 5.1.2
$\delta$	Weight of edge between Rx and accessed memory block(s)	Computed in Sect. 5.2 (Eq. 13)
$WCRT_i(f,l)$	Worst-case response time of $\tau _i$ in frame $f$ at level $\ell$	Computed in Sect. 5.1.1 (Eq. 4)
$CWCRT_{p,k}(f,l)$	Worst-case response time of tasks executing on core $p$ in the $k$-th sub-frame of frame $f$ at level $\ell$	Computed in Sect. 5.1.1, updated in Sect. 5.1.2
Design optimization—Sect. 6
$\Vert barriers\Vert _3$	3rd norm of $barriers$ for all $f\in \mathcal {F}, \ell \in \{1,\ldots ,L\}$	Computed for each candidate $\mathcal {M}_{\tau }$ (Eq. 6)
$T_0$	Initial temperature	Parameter of SA algorithm
$a$	Temperature decreasing factor	Parameter of SA algorithm
$T_{final}$	Final temperature	Parameter of SA algorithm
$time_{max}$	Time budget	Parameter of SA algorithm