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Profile-driven memory bandwidth management for accelerators and CPUs in QoS-enabled platforms

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Abstract

The proliferation of multi-core, accelerator-enabled embedded systems has introduced new opportunities to consolidate real-time systems of increasing complexity. But the road to build confidence on the temporal behavior of co-running applications has presented formidable challenges. Most prominently, the main memory subsystem represents a performance bottleneck for both CPUs and accelerators. And industry-viable frameworks for full-system main memory management and performance analysis are past due. In this paper, we propose our Envelope-aWare Predictive model, or E-WarP for short. E-WarP is a methodology and technological framework to: (1) analyze the memory demand of applications following a profile-driven approach; (2) make realistic predictions on the temporal behavior of workload deployed on CPUs and accelerators; and (3) perform saturation-aware system consolidation. This work aims at providing the technological foundations as well as the theoretical grassroots for truly workload-aware analysis of real-time systems. This work combines traditional CPU-centric bandwidth regulation techniques with state-of-the-art hardware support for memory traffic shaping via the ARM QoS extensions. We make three key observations. First, our profile-driven methodology achieves, on average, 6% over-prediction on the runtime of bandwidth-regulated applications. Second, we experimentally validate that the calculated bounds hold system-wide if the main memory subsystem operates below saturation. Third, we show that the E-WarP methodology is practical even when applications exhibit input-dependent memory access patterns. We provide a full implementation of our techniques on a commercial platform (NXP S32V234).

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Notes

  1. Contributions indicated with a * are new additions in the journal extension.

  2. This was required to overcome the lack of a PSCI firmware provided by the vendor to control CPU shutdown.

  3. https://github.com/rntmancuso/jailhouse-rt

  4. The DRAM operates at half the frequency of the CPUs.

  5. Figure 15b, c: original photos by Alexander Klein and Stefan Wernthaler, respectively, from https://www.stereoscopy.com/; Figure 15e, f: original video frames from the Visual Tracker Benchmark, respectively Basketball and CarScale data sets available at http://cvlab.hanyang.ac.kr/tracker_benchmark/datasets.html. The original photos have been scaled and/or cropped to match the same resolution and aspect ratios as the default SD-VBS image files.

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Acknowledgements

The material presented in this paper is based upon work supported by the National Science Foundation (NSF) under Grant Number CCF-2008799. The work was also supported through the Red Hat Research program. Any opinions, findings, and conclusions or recommendations expressed in this publication are those of the authors and do not necessarily reflect the views of the NSF.

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Authors and Affiliations

  1. Boston University, Boston, USA

    Parul Sohal & Renato Mancuso

  2. University of Illinois at Urbana-Champaign, Champaign, USA

    Rohan Tabish

  3. Red Hat, Raleigh, USA

    Ulrich Drepper

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  1. Parul Sohal
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  2. Rohan Tabish
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  4. Renato Mancuso
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Correspondence to Parul Sohal.

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Sohal, P., Tabish, R., Drepper, U. et al. Profile-driven memory bandwidth management for accelerators and CPUs in QoS-enabled platforms. Real-Time Syst 58, 235–274 (2022). https://doi.org/10.1007/s11241-022-09382-x

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