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Legitimate Skew Clock Routing with Buffer Insertion

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Abstract

In this paper, we propose a new quick and effective legitimate skew clock routing with buffer insertion algorithm. We analyze the optimal buffer position in the clock path, and conclude the sufficient condition and heuristic condition for buffer insertion in clock net. During the routing process, this algorithm integrates buffer insertion and node merging together, and performs them in parallel. Compared with the method of buffer insertion after zero skew clock routing, our method improves the maximal clock delay by at least 48%. Compared with legitimate skew clock routing algorithm with no buffer, this algorithm further decreases the total wire length and gets reductions from 42 to 82% in maximal clock delay. The experimental results show that our algorithm is quick and effective.

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Authors and Affiliations

  1. Department of Computer Science & Technology, Tsinghua University, Beijing, 100084, China

    Xinjie Wei, Yici Cai, Meng Zhao & Xianlong Hong

Authors
  1. Xinjie Wei
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  2. Yici Cai
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  3. Meng Zhao
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  4. Xianlong Hong
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Corresponding author

Correspondence to Xinjie Wei.

Additional information

Xinjie Wei received his B.Sc. degree in Computer Science from the PLA Nanjing Institute of Communications Engineering in 1993, and got M.S. degree in Computer Science from Xidian University in 1998. He is currently pursuing the Ph.D. degree at Tsinghua University. His research interests include computer network security, neural network and design automation for VLSI circuits and systems. And the major research attention is focused on VLSI physical design.

Yici Cai received BSc degree in Electronic Engineering from Tsinghua University in 1983 and received in and MS degree in Computer Science & Technology from Tsinghua University in 1986, She has been an associate professor in the Department of Computer Science & Technology, Tsinghua University. Beijing, China. Her research interests include VLSI layout theory and algorithms.

Meng Zhao has been an researcher in Semiconductor Industry Association of Beijing. She received her Bachelor of Engineering degree in Electronical Engineering from Tsinghua University, China, in 2000. She received her Master of Science degree in Computer Science from Tsinghua University, China, in 2003. Her research interests include VLSI design and CAD, Electronical material and device, VLSI verification and so on.

Xianlong Hong graduated from Tsinghua University, Beijing, China in 1964. Since 1988, he has been a professor in the Department of Computer Science Technology, Tsinghua University. His research interests include VLSI layout algorithms and DA systems. He is the fellow of IEEE and the Senior Member of Chinese Institute of Electronics.

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Wei, X., Cai, Y., Zhao, M. et al. Legitimate Skew Clock Routing with Buffer Insertion. J VLSI Sign Process Syst Sign Image Video Technol 42, 107–116 (2006). https://doi.org/10.1007/s11265-005-4184-7

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  • DOI: https://doi.org/10.1007/s11265-005-4184-7

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