Abstract
In this paper, a new systolic array for prime N-length DFT is first proposed, and then combined with Winograd Fourier Transform algorithm (WFTA) to control the increase of the hardware cost when the transform length is large. The proposed new DFT design is both fast and hardware efficient. Compared with the recently reported DFT design with computational complexity of O(log N), the proposed design saves the average number of required multiplications by 30 to 60% and reduces the average computation time by more than 2 times, when the transform length changes from 16 to 2048.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
L.W. Chang and M.Y. Chen, “A New Systolic Array for Discrete Fourier Transform,” IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 36, no. 10, 1988, pp. 1665–1666.
N.R. Murthy and M.N.S. Swamy, “On the Real-Time Computation of DFT and DCT Through Systolic Architectures,” IEEE Transctions on Signal Processing, vol. 42, no. 4, 1994, pp. 988–991.
D.C. Kar and V.V. Bapeswara Rao, “A New Systolic Realization for the Discrete Fourier Transform,” IEEE Transactions on Signal Processing, vol. 41, no. 5, 1993, pp. 2008–2010.
C.M. Liu and C.W. Jen, “A New Systolic Array Algorithm for Discrete Fourier Transform,” in Proc. IEEE International Conference on Circuits and Systems, 1991, pp. 2212–2215.
H.S. Silverman, “An Introduction to Programming the Winograd Fourier Transform Algorithm,” IEEE Trans. Acoustics, Speech, and Signal Processing, vol. ASSP-25, no. 2, 1977, pp. 152–165.
C.-H. Chan, C.-L. Wang, and Y.-T. Chang, “Efficient VLSI Architectures for Fast Computation of the Discrete Fourier Transform and its Inverse,” IEEE Trans. on Signal Processing, vol. 48, 2000, pp. 3206–3216.
D.F. Chiper, M.N.S. Swamy, M.O. Ahmad, and T. Stouraitis, “A Systolic Array Architecture for the Discrete Sine Transform,” IEEE Transactions on Signal Processing, vol. 50, no. 9, 2002, pp. 2347–2354.
J.I. Guo, C.M. Liu, and C.W. Jen, “A New Array Architecture for Prime-Length Discrete Cosine Transform,” IEEE Trans. on Signal Processing, vol. 41, no. 1, 1993, pp. 436–442.
P. Lavoie, “A High-Speed CMOS Implementation of the Winograd Fourier Transform Algorithm,” IEEE Trans. on Signal Processing, vol. 44, no. 8, 1996, pp. 2121–2126.
R. Tolimieri, M. An, and C. Lu, Algorithms for Discrete Fourier Transform and Convolution, Springer-Verlag, 1989.
J.I. Guo, C.-M. Liu, and C.-W. Jen, “The Efficient Memory Based VLSI Array Designs for DFT and DCT,” IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 39, no. 10, 1992, pp. 723–733.
T.S. Chang, J.I. Guo, and Chein-Wein, “Hardware-Efficient DFT Designs with Cyclic Convolution and Subexpression Sharing,” IEEE Transactions on Circuits and systems-II: Analog and Digital Signal Processing, vol. 47, no. 9, 2000, pp. 886–892.
Author information
Authors and Affiliations
Corresponding author
Additional information
Chao Cheng received his MSEE degree from Huazhong University of Science and Technology, Wuhan, China, in 2001. With three years industrial experience as a digital communication engineer from VIA Technologies, he is now pursuing his Ph.D. degree at the University of Minnesota, Twin Cities, MN.
His present research interest is in VLSI digital signal processing algorithms and their implementation.
Keshab K. Parhi received his B.Tech., MSEE, and Ph.D. degrees from the Indian Institute of Technology, Kharagpur, the University of Pennsylvania, Philadelphia, and the University of California at Berkeley, in 1982, 1984, and 1988, respectively. He has been with the University of Minnesota, Minneapolis, since 1988, where he is currently Distinguished McKnight University Professor in the Department of Electrical and Computer Engineering.
His research addresses VLSI architecture design and implementation of physical layer aspects of broadband communications systems.
He is currently working on error control coders and cryptography architectures, high-speed transceivers, and ultra wideband systems.
He has published over 400 papers, has authored the text book VLSI Digital Signal Processing Systems (Wiley, 1999) and coedited the reference book Digital Signal Processing for Multimedia Systems (Marcel Dekker, 1999).
Dr. Parhi is the recipient of numerous awards including the 2004 F.E. Terman award by the American Society of Engineering Education, the 2003 IEEE Kiyo Tomiyasu Technical Field Award, the 2001 IEEE W.R.G. Baker prize paper award, and a Golden Jubilee award from the IEEE Circuits and Systems Society in 1999.
He has served on the editorial boards of the IEEE TRANSACTIONS ON CAS, CAS-II, VLSI Systems, Signal Processing, Signal Processing Letters, and Signal Processing Magazine, and currently serves as the Editor-in-Chief of the IEEE Trans. on Circuits and Systems---I (2004--2005 term), and serves on the Editorial Board of the Journal of VLSI Signal Processing.
He has served as technical program cochair of the 1995 IEEE VLSI Signal Processing workshop and the 1996 ASAP conference, and as the general chair of the 2002 IEEE Workshop on Signal Processing Systems. He was a distinguished lecturer for the IEEE Circuits and Systems society during 1996--1998. He is a Fellow of IEEE (1996).
An erratum to this article is available at http://dx.doi.org/10.1007/s11265-006-8456-7.
Rights and permissions
About this article
Cite this article
Cheng, C., Parhi, K.K. Hardware Efficient Fast Computation of the Discrete Fourier Transform. J VLSI Sign Process Syst Sign Image Video Technol 42, 159–171 (2006). https://doi.org/10.1007/s11265-005-4187-4
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11265-005-4187-4