Abstract
A new array type parallel scheme for an FIR digital filter is presented in this paper. The proposed scheme is based on the structure of the carry-save array multiplier where each cell implements the computation of an FIR filter at the bit-level. This structure leads to latency independent of the number of the filter taps. The proposed scheme is pipelined at the bit-level, is systolic at the cell-level and requires less hardware than other schemes based on discrete multipliers.
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Paraskevas Kalivas received his Diploma and Ph.D. degree in electrical and computer engineering from the National Technical University of Athens, Greece, in 1990 and 2000 respectively.
His research interests include computer arithmetic and efficient realization of arithmetic circuits and digital filters.
Vassilis Vassilakis received his Diploma in electrical and computer engineering from NationalTechnical University of Athens, Greece, in 1997. He isworking toward the Ph.D. degree in electrical engineering at National Technical University of Athens.
His research interests include efficient circuit implemenation of DSP algorithms and java processor architectures.
Chris Meletis received his Diploma in electrical and computer engineering from National Technical University of Athens in 1997. Currently, he is working toward the Ph.D. degree in electrical engineering at National Technical University of Athens.
His research interests include multirate filter banks, digital filter design and their efficient realization.
Kiamal Z. Pekmestzi received his Diploma in electrical engineering from the National Technical University of Athens, Greece, in 1975. From 1975 to 1981, he was a research fellow in the Electronics Department of the Nuclear Research Center ”Demokritos“. He received his Ph.D. in electrical engineering from the University of Patras, Greece, in 1981.
From 1983 to 1985, he was a professor at the Higher School of Electronics in Athens. Since 1985, he has been with the National Technical University of Athens, where he is currently a professor. His research interests include computer arithmetic, VLSI digital filters and VLSI design automation.
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Kalivas, P., Vassilakis, V., Meletis, C. et al. A New Low Latency Parallel FIR Filter Scheme. J VLSI Sign Process Syst Sign Image Video Technol 39, 313–322 (2005). https://doi.org/10.1007/s11265-005-4847-4
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DOI: https://doi.org/10.1007/s11265-005-4847-4