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New Models of Prefix Adder Topologies

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Abstract

This paper introduces a variety of approaches for assessing logarithmic-depth parallel prefix adders: a delay model based on a slight modification to the Logical Effort methodology is derived; a simple area model based on wire pitch is described; a new parameter, span(i), is defined that provides a mechanism for determining cell count and whether a prefix tree exhibits idempotency. The models are tested against Knowles’ Family of Adders and found to give results that are within 5% of those reported by Knowles, as well as allowing a full assessment of the family to be made. Finally, the delay and area models are used to assess the Flagged Prefix Adder, an enhanced adder capable of computing absolute differences.

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  1. Neil Burgess

    Present address: Icera Semiconductor, 2520 The Quadrant, Aztec West, Almondsburv, Bristol, BS32 4AQ

Authors and Affiliations

  1. Division of Electronics, School of Engineering, Cardiff University, Queen’s Buildings, The Parade, PO Box 689, Cardiff CF24 3TF, UK

    Neil Burgess

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  1. Neil Burgess
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Correspondence to Neil Burgess.

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Neil Burgess Ph.D., M.Sc., B.Sc., was awarded a PhD by Southampton University (U.K.) in 1986 for his work on graph theoretic techniques to model failure mechanisms in MOS VLSI circuits. He then spent two years designing DSP VLSI chips at GEC’s Hirst Research Labs in Wembley, London, before moving to academia to lecture in Microelectronic Systems, first at Brunel University, London, then for 6 years at the University of Adelaide, Australia. In 1996, he was appointed Director of the University of Adelaide’s Centre for High-Performance Technology and Systems, whose major research activity was centred on the design of high-performance digital microelectronic circuits. In 1999, he returned to the U.K. to take up a Professorial Research Fellowship in the Division of Electronics at Cardiff University’s School of Engineering. His research activities in these posts have revolved around digital VLSI design in both CMOS and GaAs, and high-speed arithmetic processing, expanding this work to address applications including cryptography, image compression, and DSP. In October 2003, he left the academic sector to join Icera Semiconductor, a silicon start-up company whose design office is in Bristol, UK. He has published over 80 papers and is an associate editor of the IEEE Transactions of Computers. He co-chaired the 14th and 15th IEEE Symposia on Computer Arithmetic (in 1999 and 2001), the 13th IEEE International Conference on Application-Specific Systems Architectures and Processors (2002), and the 37th and 38th IEEE Asilomar Conference on Signals, Systems and Computers (2003 and 2004).

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Burgess, N. New Models of Prefix Adder Topologies. J VLSI Sign Process Syst Sign Image Video Technol 40, 125–141 (2005). https://doi.org/10.1007/s11265-005-4942-6

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  • DOI: https://doi.org/10.1007/s11265-005-4942-6

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