Abstract
H.264/AVC also known as MPEG 4 part 10 or JVT, is a recently established video coding standard by the Joint Video Team (JVT) of the ISO/IEC MPEG and ITU-T VCEG. The main goal of the paper is to give a broader understanding of the design considerations for the transform and quantization blocks from H.264/AVC, by presenting area and speed optimized implementations of these blocks. The area optimized design can be used in low performance applications like mobile devices, while the speed optimized designs can be used in high definition encoders. Various designs with these blocks were synthesized with 0.18 μm TSCM technology and were also implemented on a Xilinx FPGA. The resulting gate counts were anywhere from 294 to 47,762 gates and the throughput was anywhere from 6 to 2,552 M pixels/s depending on block and optimization. In addition, a system on a programmable chip implementation of the DCT and quantization blocks is presented, which uses the Xilinx Virtex II-Pro’s FPGA and its Power PC. Using this system it is possible to process 0.8 M pixels/s.
Similar content being viewed by others
References
K. Sayood, Introduction to Data Compression, Morgan Kaufman, San Mateo, CA, 2000.
H. S. Malvar, A. Hallapuro, M. Karaczewicz, and L. Kerofsky, “Low-Complexity Transform and Quantization in H.264/AVC,” IEEE Trans. Circuits Syst. Video Technol., vol. 13, no. 7, July 2003.
I. E. G. Richardson, H.264/MPEG-4 Part 10: Transform & Qantization. [Online]. Available: http://www.vcodex.com, 2002.
M. Horowitz, A. Joch, F. Kossentini, and A. Hallapuro, “H.264/AVC Baseline Profile Decoder Complexity Analysis,” IEEE Trans. Circuits Syst. Video Technol., vol. 13, no. 7, July 2003.
A. Hallapuro and M. Karczewicz, “Low Complexity Transform and Quantization-Part 1: Basic Implementation,” February 2001, JVT Document JVT-B038.
T. Wiegand and G. Sullivan, Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification. [Online]. Available: ftp://ftp.imtc-files.org/jvt-experts, 2003.
T.-C. Wang, Y.-W. Huang, H.-C. Fang, and L.-G. Chen, “Parallel 4 × 4 2D transform and inverse transform architecture for MPEG-4 AVC/H.264,” in Proceedings of the 2003 International Symposium on Circuits and Systems, vol. 2, May 2003, pp. II-800-II-803.
A. M. Patino, M. Peiro, F. Ballester, and G. Paya, “2D-DCT on FPGA by Polynomial Transformation in Two-Dimentions,” in Proceedings of the 2004 International Symposium on Circuits and Systems, vol. 3, May 2004, pp. III-365-III-368.
M. Fu, G. Jullien, V. Dimitrov, and M. Ahmadi, “A Low-Power DCT IP Core Based on 2D Algebraic Integer Encoding,” in Proceedings of the 2004 International Symposium on Circuits and Systems, vol. 2, May 2004, pp. II-765-II-768.
Author information
Authors and Affiliations
Corresponding authors
Rights and permissions
About this article
Cite this article
Kordasiewicz, R., Shirani, S. On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC. J VLSI Sign Process Syst Sign Image Video Technol 47, 93–102 (2007). https://doi.org/10.1007/s11265-006-0030-9
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11265-006-0030-9