Abstract
There are many applications in which particle filters outperform traditional signal processing algorithms. Some of these applications include tracking, joint detection and estimation in wireless communication, and computer vision. However, particle filters are not used in practice for these applications mainly because they cannot satisfy real-time requirements. This paper presents an efficient resampling architecture for parallel particle filtering. The proposed architecture is flexible such that it supports various modes of parallel resampling operations with up to four processing elements. The resampling algorithm is developed in order to compensate for possible error caused by finite precision quantization in the resampling step. Communication between the processing elements after resampling is identified as an implementation bottleneck, and therefore, concurrent buffering is incorporated in order to speed up communication of particles among processing elements. The flexible resampling mechanism is implemented in 0.35 μ m CMOS process and its complexity and performance are analyzed.
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Sangjin Hong received the B.S and M.S degrees in EECS from the University of California, Berkeley. He received his Ph.D in EECS from the University of Michigan, Ann Arbor. He is currently with the department of Electrical and Computer Engineering at State University of New York, Stony Brook. Before joining SUNY, he has worked at Ford Aerospace Corp. Computer Systems Division as a systems engineer. He also worked at Samsung Electronics in Korea as a technical consultant. His current research interests are in the areas of low power VLSI design of multimedia wireless communications and digital signal processing systems, reconfigurable SoC design and optimization, VLSI signal processing, and low-complexity digital circuits. Prof. Hong served on numerous Technical Program Committees for IEEE conferences. Prof. Hong is a Senior Member of IEEE.
Shu-Shin Chin was born in Kaohsiung, Taiwan, ROC, in 1974. He received his M.S. and Ph.D degrees in electrical and computer engineering from Stony Brook University – State University of New York in 1999 and 2004, respectively. His research interests include low-power digital circuits, and coarse-grained reconfigurable architectures for high-performance DSP systems.
Miodrag Bolić received the B.S. and M.S. degrees in electrical engineering from the University of Belgrade, Yugoslavia, in 1996 and 2001, respectively, and his Ph.D. degree in electrical engineering from Stony Brook University, NY, USA. He is currently with the School of Information Technology and Engineering at the University of Ottawa, Canada. From 1996 to 2000 he was Research Associate with the Institute of Nuclear Science Vinĉa, Yugoslavia. From 2001 to 2004 he worked part-time at Symbol Technologies Inc., NY, USA. His research is related to VLSI architectures for digital signal processing and signal processing in wireless communications and tracking.
Petar M. Djurić received his B.S. and M.S. degrees in electrical engineering from the University of Belgrade, in 1981 and 1986, respectively, and his Ph.D. degree in electrical engineering from the University of Rhode Island, in 1990. From 1981 to 1986 he was Research Associate with the Institute of Nuclear Sciences, Vinĉa, Belgrade. Since 1990 he has been with Stony Brook University, where he is Professor in the Department of Electrical and Computer Engineering. He works in the area of statistical signal processing, and his primary interests are in the theory of modeling, detection, estimation, and time series analysis and its application to a wide variety of disciplines including wireless communications and bio-medicine. Prof. Djurić has served on numerous Technical Committees for the IEEE and SPIE and has been invited to lecture at universities in the US and overseas. He is the Area Editor of Special Issues of the Signal Processing Magazine, the Treasurer of the IEEE Signal Processing Conference Board, and Associate Editor of the IEEE Transactions on Signal Processing. He is also the Chair elect of the IEEE Signal Processing Society Committee on Signal Processing—Theory and Methods, and an Editorial Board member of Digital Signal Processing, the EURASIP Journal on Applied Signal Processing and the EURASIP Journal on Wireless Communications and Networking. Prof. Djurić is a Member of the American Statistical Association and the International Society for Bayesian Analysis.
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Hong, S., Chin, SS., Djurić, P.M. et al. Design and Implementation of Flexible Resampling Mechanism for High-Speed Parallel Particle Filters. J VLSI Sign Process Syst Sign Image Video Technol 44, 47–62 (2006). https://doi.org/10.1007/s11265-006-5919-9
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DOI: https://doi.org/10.1007/s11265-006-5919-9