Abstract
In this paper, we study the performance impact of dynamic hardware reconfigurations for current reconfigurable technology. As a testbed, we target the Xilinx Virtex II Pro, the Molen experimental platform and the MPEG2 encoder as the application. Our experiments show that slowdowns of up to a factor 1000 are observed when the configuration latency is not hidden by the compiler. In order to avoid the performance decrease, we propose an interprocedural optimization that minimizes the number of executed hardware configuration instructions taking into account constraints such as the “FPGA-area placement conflicts” between the available hardware configurations. The presented algorithm allows the anticipation of hardware configuration instructions up to the application’s main procedure. The presented results show that our optimization produces a reduction of 3 to 5 order of magnitude of the number of executed hardware configuration instructions. Moreover, the optimization allows to exploit up to 97% of the maximal theoretical speedup achieved by the reconfigurable hardware execution.
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Panainte, E.M., Bertels, K. & Vassiliadis, S. Interprocedural Compiler Optimization for Partial Run-Time Reconfiguration. J VLSI Sign Process Syst Sign Image Video Technol 43, 161–172 (2006). https://doi.org/10.1007/s11265-006-7268-0
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DOI: https://doi.org/10.1007/s11265-006-7268-0