Skip to main content

Advertisement

SpringerLink
Log in

HIBI Communication Network for System-on-Chip

  • Published:
Journal of VLSI signal processing systems for signal, image and video technology Aims and scope Submit manuscript

Abstract

This paper presents a communication network targeted for complex system-on-chip (SoC) and network-on-chip (NoC) designs. The Heterogeneous IP Block Interconnection (HIBI) aims at maximum efficiency and minimum energy per transmitted bit combined with quality-of-service (QoS) in transfers. Other features include support for hierarchical topologies with several clock domains, flexible scalability, and runtime reconfiguration of network parameters. HIBI is intended for integrating coarse-grain components such as intellectual property (IP) blocks that have size of thousands of gates.HIBI has been implemented in VHDL and SystemC and synthesized on several CMOS technologies and on FPGA. A 32-bit wrapper requires 5400 gates and runs with 315 MHz on 0.18 μ m technology which shows that only minimal area overhead is paid for the advanced features. The area and frequency results are well comparable to other NoC proposals.Furthermore, data transfers are shown to approach the maximum theoretical performance for protocol efficiency. HIBI network is accompanied with a design framework with tools for optimizing the system through automated design space exploration.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. H. Chang, L. Cooke, M. Hunt, G. Martin, A. McNelly, and L. Todd, Surviving the SoC Revolution. Norwell, MA: Kluwer Academic Publishers, 1999.

    Google Scholar 

  2. M. Keating and P. Bricaud, Reuse Methodology Manual, 2nd ed. Norwell, MA: Kluwer Academic Publishers, 1999.

    Book  Google Scholar 

  3. K. Keutzer, S. Malik, R. Newton, J. M. Rabaey, and A. Sangiovanni-Vincentelli, “System-level design: Orthogonalization of concerns and platform-based design,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 12, 2000.

  4. I. Scherson and A. Youssef, Eds., Interconnection Networks for High-Performance Parallel Computers. Los Alamitos, CA: IEEE Computer Society Press, 1994.

  5. A. Varma and C. Raghavendra, Eds., Interconnection Networks for Multiprocessors and Multicomputers Theory and Practice. Los Alamitos, CA: IEEE Computer Society Press, 1994.

  6. J. Zalewski, Ed., Interconnection Networks for Multiprocessors and Multicomputers Theory and Practice. Los Alamitos, CA: IEEE Computer Society Press, 1995.

  7. J. Park, I. Kim, S. Kim, S. Park, B. Koo, K. Shin, K. Seo, and J. Cha, “MPEG-4 video codec on an ARM and AMBA,” in Workshop and Exhibition on MPEG-4, San Jose, CA, 2001, pp. 95–98.

  8. S. Dutta, R. Jensen, and A. Rieckmann, “Viper: A multiprocessor SOC for advanced set-top box and digital TV systems,” IEEE Design and Test of Computers, vol. 18, no. 5, 2001, pp. 21–31.

    Article  Google Scholar 

  9. A. Jalabert, S. Murali, L. Benini, and G. D. Micheli, “Xpipescompiler: a tool for instantiating application specific networks on chip,” in DATE, 2004, pp. 884–889.

  10. K. K. Ryu and V. J. Mooney III, “Automated bus generation for multiprocessor SoC design,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 11, 2004, pp. 1531–1549.

    Article  Google Scholar 

  11. K. Kuusilinna, T. Hämäläinen, P. Liimatainen, and J. Saarinen, “Low-latency interconnection for IP-block based multimedia chips,” in PDCN, Brisbane, Australia, 1998, pp. 411–416.

  12. V. Lahtinen, K. Kuusilinna, T. Kangas, and T. Hämäläinen, “Interconnection scheme for continuous-media systems-on-chip,” Microprocessors and Microsystems, vol. 26, no. 3, 2002, pp. 123–138.

    Article  Google Scholar 

  13. D. Sylvester and K. Keutzer, “Impact of small process geometries on microarchitectures in systems on a chip,” Proc. IEEE, vol. 89, no. 4, 2001, pp. 467–489.

    Article  Google Scholar 

  14. E. Salminen, K. Kuusilinna, and T. Hämäläinen, “Comparison of hardware IP components for system-on-chip,” in Intl. Symposium on System-on-Chip, Tampere, Finland, 2004, pp. 69–73.

  15. AMBA Specification, Rev. 2.0. ed., Arm Limited, 1999.

  16. Sonics MicroNetworks Technical Overview Revision, A21-1 ed., Sonics Inc., 2000.

  17. E. Salminen, V. Lahtinen, K. Kuusilinna, and T. Hämäläinen, “Overview of bus-based system-on-chip interconnections,” in ISCAS, vol. 2, Scottsdale, AZ, 2002, pp. 372–375.

    Google Scholar 

  18. K. Lahiri, A. Raghunathan, and S. Dey, “Design space exploration for optimizing on-chip communication architectures,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 6, pp. 952–961, 2004.

    Article  Google Scholar 

  19. L. Benini and G. de Micheli, “Networks on chips: A new SoC paradigm,” Computer, vol. 35, no. 1, 2002, pp. 70–78.

  20. A. Jantsch and H. Tenhunen, Eds., Networks on Chip. Dordrecht, The Netherlands: Kluwer Academic Publishers, 2003.

  21. P. Guerrier and A. Greiner, “A generic architecture for on-chip packet-switched interconnections,” in DATE, Paris, France, 2000, pp. 250–256.

  22. A. Andriahantenaina and A. Greiner, “Micro-network for SoC: Implementation of a 32-port SPIN network,” in DATE, Munich, Germany, 2003, pp. 11, 128–11, 129.

  23. P. P. Pande, C. Grecu, A. Ivanov, and R. Saleh, “Switch-based interconnect architecture for future systems on chip,” in SPIE, VLSI Circuits and Systems, vol. 5117, Maspalomas, Gran Canaria, Spain, 2003, pp. 228–237.

  24. H. Kariniemi and J. Nurmi, “Reusable XGFT interconnect IP for network-on-chip implementations,” in Intl. Symposium on System-on-Chip, Tampere, Finland, 2004, pp. 94–102.

  25. T. Valtonen, T. Nurmi, J. Isoaho, and H. Tenhunen, “An autonomous error-tolerant cell for scalable network-on-chip architectures,” in Norchip, Kista, Sweden, 2001, pp. 198–203.

  26. T. Bartic, J.-Y. Mignolet, V. Nollet, T. Marescaux, D. Verkest, S. Vernalde, and R. Lauwereins, “Highly scalable network on chip for reconfigurable systems,” in Intl. Symposium on System-on-Chip, Tampere, Finland, 2003, pp. 78–82.

  27. D. Sigüenza-Tortosa, T. Ahonen, and J. Nurmi, “Issues in the development of a practical NoC: the Proteo concept,” Integration, the VLSI Journal, vol. 38, no. 1, 2004, pp. 95–105.

    Article  Google Scholar 

  28. E. Nilsson, “Design and implementation of a hot-potato switch in network on chip,” Master’s thesis, Royal Institute of Technology (KTH), Stockholm, Sweden, 2002.

  29. J. Hu and R. Marculescu, “Dyad - smart routing for networks-on-chip,” in DAC, San Diego, CA, 2004, pp. 260–263.

  30. E. Bolotin, I. Gidon, R. Ginosar, and A. Kolodny, “QNoC: QoS architecture and design process for network on chip,” Journal of Systems Architecture, vol. 50, no. 2–3, 2004, pp. 105–128.

    Article  Google Scholar 

  31. E. Rijpkema, K. Goossens, A. Radulescu, J. Dielisen, J. van Meerbergen, P. Wielage, and E. Waterlander, “Trade offs in the design of a router with both guaranteed and best-effort services for network on chip (extended version),” IEE Proc. Computers and Digital Techniques, vol. 150, no. 5, 2003, pp. 294–302.

    Article  Google Scholar 

  32. P. Vellanki, N. Banerjee, and K. S. Chatha, “Quality-of-service and error control techniques for mesh-based network-on-chip architectures,” Integration, the VLSI Journal, vol. 38, no. 3, 2005, pp. 353–382.

    Article  Google Scholar 

  33. F. Moraes, N. Calazans, A. Mello, L. Moller, and L. Ost, “Hermes: an infrastructure for low area overhead packet-switching networks on chip,” Integration, the VLSI Journal, vol. 38, no. 1, 2004, pp. 69–93.

  34. C. A. Zeferino, M. E. Kreutz, L. Carro, and A. A. Susin, “A study on communication issues for system-on-chip,” in SBCCI, Porto Alegre, Brazil, 2002, pp. 121–126.

  35. E. Salminen, T. Kangas, J. Riihimäki, V. Lahtinen, K. Kuusilinna, and T. D. Hämäläinen, “Benchmarking mesh and hierarchical bus networks in system-on-chip context,” in SAMOS, accepted for publication, Samos, Greece, 2005, pp. 354–363 .

  36. M.-C. Chiang and G. S. Sohi, “Evaluating design choices for sha- red bus multiprocessors in a throughput-oriented environment,” IEEE Trans. Computers, vol. 41, no. 3, 1992, pp. 297–317.

  37. Open Core Protocol Specification, Release 1.0, OCP-IP Alliance, Portland, OR, 2001.

  38. T. Kangas, V. Lahtinen, K. Kuusilinna, and T. Hämäläinen, “System-on-chip communication optimization with bus monitoring,” in DDECS, Brno, Czech Republic, 2002, pp. 304–309.

    Google Scholar 

  39. ARM7 Thumb Family Flyer, Arm Limited, 2003.

  40. T. Kangas, E. Salminen, K. Kuusilinna, T. Hämäläinen, and J. Saarinen, “Flexible architecture for system-on-chip video codec,” in ISPACS, Honolulu, Hawaii, 2001, pp. 216–221.

  41. J. Riihimäki, P. Kukkala, E. Salminen, M. Hännikäinen, K.Kuusilinna, and T. Hämäläinen, “Practical distributed simulation of a network of wireless terminals,” in Intl. Symposium on System-on-Chip, Tampere, Finland, 2004, pp. 49–52.

    Google Scholar 

  42. E. Salminen, A. Kulmala, and T. Hämäläinen, “HIBI-based multiprocessor SoC on FPGA,” in ISCAS, Kobe, Japan, 2005, pp. 3351–3354.

  43. O. Lehtoranta, E. Salminen, A. Kulmala, M. Hännikäinen, and T. Hämäläinen, “A parallel MPEG-4 encoder for FPGA based multiprocessor SoC,” in FPL, accepted for publication, Tampere, Finland, 2005, pp. 380–385.

  44. T. Kangas, J. Riihimäki, E. Salminen, V. Lahtinen, H. Orsila, K. Kuusilinna, and T. Hämäläinen, “A communication-centric design flow for HIBI-based SoCs,” in SAMOS, Samos, Greece, 2004, pp. 474–483.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Tampere University of Technology, P.O. Box 553, FIN-33101, Tampere, Finland

    Erno Salminen, Tero Kangas & Timo D. Hämäläinen

  2. Nokia Technology Platforms, P.O. Box 88, FIN-33731, Tampere, Finland

    Jouni Riihimäki

  3. Nokia Research Center, P.O. Box 100, FIN-33721, Tampere, Finland

    Vesa Lahtinen & Kimmo Kuusilinna

Authors
  1. Erno Salminen
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Tero Kangas
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Timo D. Hämäläinen
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Jouni Riihimäki
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Vesa Lahtinen
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. Kimmo Kuusilinna
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Erno Salminen.

Additional information

Erno Salminen Tampere University of Technology (TUT), Finland.Currently he is working towards his PhD degree in the Institute of Digital and Computer Systems (DCS) at TUT. His main research interests are digital systems design and communication issues in SoCs.

Tero KangasTampere University of Technology (TUT), Finland.Since 1999 he has been working as a research scientist in the Institute of Digital and Computer Systems (DCS) at TUT. Currently he is working towards his PhD degree and his main research topics are system architectures and SoC design methodologies in multimedia applications.

Timo D. Hämäaläainen Tampere University of Technology (TUT), Finland. He was nominated to full professor at TUT/Institute of Digital and Computer Systems in 2001. He heads the DACI research group that focuses on three main research areas: wireless sensor networks, high-performance multi-DSP and hardware based video encoding, and design flow tools for heterogeneous MP-SoC platforms.

Jouni Riihiämki Tampere University of Technology (TUT), Finland. Currently he is working as a senior design engineer at Nokia Technlogy Platforms. He is also working towards his PhD degree. His research interests include SoC design and verification methodologies.

Vesa Lahtinen received his M.Sc. and Ph.D. from TUT in 1998 and 2004, respectively. In TUT, his main research areas were system-on-chips and their interconnects. Currently, Dr. Lahtinen is a Senior Research Engineer in the Computing Architectures Laboratory of Nokia Research Center (NRC) concentrating on architecture modeling and, specifically, memory architectures.

Kimmo Kuusilinna Tampere University of Technology (TUT), Finland. His main research interests include system-level design and verification, on-chip interconnections, and parallel memories. Currently he is working as a senior research engineer at the Nokia Research Center.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Salminen, E., Kangas, T., Hämäläinen, T.D. et al. HIBI Communication Network for System-on-Chip. J VLSI Sign Process Syst Sign Image Video Technol 43, 185–205 (2006). https://doi.org/10.1007/s11265-006-7270-6

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11265-006-7270-6

Keywords

Search

Navigation