Abstract
Current rapid synthesis approaches for reusable dedicated hardware components (cores) for digital signal processing systems are ineffective since they fail to capture and exploit the manner in which the resulting components are used as part of a heterogeneous system. This leads to counter-productive core redesign for each use of the core. This paper presents a solution to this issue which combines a novel but intuitive system modeling technique and associated core generation and integration methodology which generates reuable core architectures which may be optimised via algorithm level transformations. For an example design problem, these provide an effective rapid core synthesis and implementation exploration flow which allows a factor 3.9 throughput increase with no extra hardware expense.
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John McAllister received a first honours B.Eng degree in Electrical and Electronic Engineering and the degree of PhD from Queen’s University Belfast, UK in 2001 and 2004 respectively.From October 2004 to July 2005 he was a Postdoctoral Research Assistant in the Programmable Systems Laboratory in the System on Chip research group in the Institute for Electronics, Communication and Information Technology (ECIT) at Queen’s University Belfast.In July 2005 he was appointed to a lectureship in SoC technology in the International Centre for System-on-Chip and Advanced Microwireless (SoCAM) project at ECIT.
Roger Woods received the degree of B.Sc with Honours in Electrical and Electronic Engineering and degree of Ph.D. from the Queen’s University of Belfast, UK in 1985 and 1990 respectively. From 2003, he has been a Professor at the same university and leads the programmable systems and networks laboratory there. His main research interests are programmable hardware systems using FPGAs, design tools for heterogeneous platforms and low power VLSI. He has published over 120 papers in the area of VLSI and DSP, holds two patents and serves on numerous technical program committees including Workshop on Signal Processing Systems, Field Programmable Logic and Field Programmable Technology. He is a member the IEEE Signal Processing Society Technical Committee for the Design and Implementation of Signal Processing Systems and chair of the IEE Professional Network on Microelectronics and Embedded Systems.
Richard Walke received his Ph.D. from Warwick University in 1998 for work on arithmetic, architectures and implementations of adaptive weight calculation in ASIC. Subsequently he worked on the implementation of a range of DSP algorithms in FPGA, specialising in floating-point arithmetic, digital receivers and adaptive beamformers on FPGA. In recent years he has lead work to address the design of heterogeneous systems employing both processor and FPGA. Last year he moved to Xilinx, and is now responsible for the development of their floating-point IP solution.
Darren Reilly received first honours B.Eng. Degree in Electronic and Software Engineering from the Queen’s University Belfast in 2002. He is currently pursuing a Ph.D. in Queen’s University Belfast due to finish in September 2005. His research interests lie in the rapid development of efficient architectures for FPGA as part of a system level design flow.
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Mcallister, J., Woods, R., Walke, R. et al. Multidimensional DSP Core Synthesis for FPGA. J VLSI Sign Process Syst Sign Image Video Technol 43, 207–221 (2006). https://doi.org/10.1007/s11265-006-7271-5
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DOI: https://doi.org/10.1007/s11265-006-7271-5