Skip to main content
SpringerLink
Log in

Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting

  • Published:
Journal of VLSI signal processing systems for signal, image and video technology Aims and scope Submit manuscript

Abstract

Today’s Application Specific Instruction-set Processor (ASIP) design methodology often employs centralized Architecture Description Language (ADL) processor models, from which software tools, such as C compiler, assembler, linker, and instruction-set simulator, can be automatically generated. Among these tools, the C compiler is becoming more and more important. However, the generation of C compilers requires high-level architecture information rather than low-level details needed by simulator generation. This makes it particularly difficult to include different aspects of the target architectureinto one single model, and meanwhile keeping consistency.

This paper presents a modeling style, which is able to capture high- and low-level architectural information at the same time and make it possible to drive both the C compiler and the simulator generation without sacrificing the modeling flexibility. The proposed approach has been successfully applied to model a number of contemporary, real-world processor architectures.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. A. Hoffmann, R. Leupers, and H. Meyr. Architecture Exploration for Embedded Processors with LISA. Kluwer Academic Publishers, Boston, Jan. 2003. ISBN 1-4020-7338-0.

  2. G. Braun, A. Nohl, W. Sheng, J. Ceng, M. Hohenauer, H. Scharwaechter, R. Leupers, and H. Meyr. A Novel Approach for Flexible and Consistent ADL-driven ASIP Design. Proc. of the Design Automation Conference (DAC), Mar. 2004.

  3. S. Bashford, U. Bieker, B. Harking, R. Leupers, P. Marwedel, A. Neumann, and D. Voggenauer. The MIMOLA Language, Version 4.1. Reference Manual, Department of Computer Science 12, Embedded System Design and Didactics of Computer Science, 1994.

  4. R. Leupers and P. Marwedel. A BDD-based frontend for retargetable compilers. In Proc. of the European Design and Test Conference (ED & TC), pages 239–243, 1995.

  5. G. Hadjiyiannis, S. Hanono, and S. Devadas. ISDL: An Instruction Set Description Language for Retargetability. In Proc. of the Design Automation Conference (DAC), Jun. 1997.

  6. Silvina Hanono and Srinivas Devadas. Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator. In Design Automation Conference, pages 510–515, 1998.

  7. A. Fauth, J. Van Praet, and M. Freericks. Describing Instruction Set Processors Using nML. In Proc. of the European Design and Test Conference (ED & TC), Mar. 1995.

  8. A. Halambi, P. Grun, V. Ganesh, A. Khare, N. Dutt, and A. Nicolau. EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability. In Proc. of the Conference on Design, Automation & Test in Europe (DATE), Mar. 1999.

  9. EXPRESSION User Manual (version 1.0) http://www.ics.uci.edu/~express/documentation.htm.

  10. A. Hoffmann, T. Kogel, A. Nohl, G. Braun, O. Schliebusch, O. Wahlen, A. Wieferink, and H. Meyr. A Novel Methodology for the Design of Application Specific Instruction Set Processors (ASIP) Using a Machine Description Language. IEEE Transactions on Computer-Aided Design, 20(11):1338–1354, Nov. 2001.

    Article  Google Scholar 

  11. CoWare Inc., www.coware.com. LISATek product family.

  12. M. Hohenauer, H. Scharwaechter, K. Karuri, O. Wahlen, T. Kogel, R. Leupers, G. Ascheid, and H. Meyr. A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models. Proc. of the Conference on Design, Automation & Test in Europe (DATE), Mar. 2004.

  13. ACE – Associated Computer Experts bv. The COSY Compiler Development System http://www.ace.nl.

  14. J. Ceng, M. Hohenauer, R. Leupers, G. Ascheid, H. Meyr, and G. Braun. C compiler retargeting based on instruction semantics models. In DATE, pages 1150–1155, 2005.

  15. A. Aho, R. Sethi, and J. Ullman. Compilers, Principles, Techniques and Tools. Addison-Wesley, Jan. 1986. ISBN 0-2011-0088-6.

  16. A. Aho, M. Ganapathi, and S. Tjiang. Code generation using tree matching and dynamic programming. IEEE Transactions on Programming Languages and Systems, 11(4):491–516, Oct. 1989.

    Article  Google Scholar 

  17. F. Homewood and P. Faraboschi. ST200: A VLIW Architecture for Media-Oriented Applications. In Microprocessor Forum, Oct. 2000.

  18. X. Nie, L. Gazsi, F. Engel, and G. Fettweis. A new network processor architecture for high-speed communications. In Proc. of the IEEE Workshop on Signal Processing Systems (SIPS), pages 548–557, Oct. 1999.

Download references

Author information

Authors and Affiliations

  1. Institute for Integrated Signal Processing Systems, Aachen University of Technology (RWTH), Sommerfeldstr. 24 WSH, Aachen, Germany

    Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid & Heinrich Meyr

  2. CoWare, Inc., Dennewartstrasse 25-27, Aachen, Germany

    Gunnar Braun

Authors
  1. Jianjiang Ceng
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Weihua Sheng
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Manuel Hohenauer
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Rainer Leupers
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Gerd Ascheid
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. Heinrich Meyr
    View author publications

    You can also search for this author in PubMed Google Scholar

  7. Gunnar Braun
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Jianjiang Ceng.

Additional information

Jianjiang Ceng received his B. Eng. Degree in Electric Engineering from Shanghai Jiaotong University, Shanghai, China, in 1999 and the M. Sc. degree in Communications Engineering from the RWTH Aachen University of Technology, Aachen, Germany, in 2003. He is currently doing his PhD in the Institute of Integrated Signal Processing System of the RWTH-Aachen. His research interests are in embedded software, retargetable compilation, code optimization, with current activity focused on the heterogeneous multi-processor compilation and system simulation.

Weihua Sheng received his M. Sc. degree in Communications Engineering from the RWTH Aachen University of Technology, Aachen, Germany, in 2003. He is currently working in Synopsys Shanghai as R& D engineer.

Manuel Hohenauer received the diploma in electrical engineering from Aachen University of Technology (RWTH), Aachen, Germany, and is currently working towards the Ph.D. degree in electrical engineering at the same university. His research interests include retargetable code generation for embedded processors with main focus on machine description generation for retargetable compilers from architectural descriptions and retargetable code optimization techniques.

Rainer Leupers received the Diploma and Ph.D. degrees in Computer Science with honors from the University of Dortmund, Germany, in 1992 and 1997. From 1997-2001 he was a senior research engineer at the Embedded Systems group at the University of Dortmund. Between 1999-2001 he was also a project manager at ICD, where he headed the development of custom C compilers and other industrial software tool projects. In 2002, Dr. Leupers joined RWTH Aachen University as a professor for Software for Systems on Silicon. His research and teaching activities revolve around software development tools, processor architectures, and electronic design automation for embedded systems, with emphasis on C compilers for application specific processors in the areas of signal processing and networking. He authored several books and numerous technical papers on software tools for embedded processors, and he served in the program committees of leading EDA and compiler conferences, including DAC, DATE, and ICCAD. Dr. Leupers received several scientific awards, including Best Paper Awards at DATE 2000 and DAC 2002.

Gerd Ascheid received the Dipl.-Ing. and Dr.-Ing. (PhD) degrees from the Aachen University in 1977 and 1984. PhD research focused on synchronization algorithms for digital receivers and their implementation using digital signal processing. This work was complemented by measurement and analysis of the non-linear behaviour of phase locked loops in noise. After the PhD he worked as Sr. Researcher at the Aachen University, continuing the research on synchronization and working on various industry consulting projects for European and US based companies. During that time he co-authored (jointly with Dr. Meyr) the book “Synchronization in Digital Communications”, published by Wiley in 1990. Since April 2003 he is heading the Institute for Integrated Signal Processing Systems jointly with Prof. Meyr.

Heinrich Meyr received his M.Sc. and Ph.D. from ETH Zurich, Switzerland. He spent over 12 years in various research and management positions in industry before accepting a professorship in Electrical Engineering at Aachen University of Technology (RWTH Aachen) in 1977. He has worked extensively in the areas of communication theory, digital signal processing and CAD tools for system level design for the last thirty years. His research has been applied to the design of many industrial products. At RWTH Aachen he is a co-director of the institute for integrated signal processing system (ISS) involved in the analysis and design of complex signal processing systems for communication applications. As well as being a Fellow of the IEEE he has served as Vice President for International Affairs of the IEEE Communications Society

Rights and permissions

Reprints and permissions

About this article

Cite this article

Ceng, J., Sheng, W., Hohenauer, M. et al. Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. J VLSI Sign Process Syst Sign Image Video Technol 43, 235–246 (2006). https://doi.org/10.1007/s11265-006-7273-3

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11265-006-7273-3

Keywords

Search

Navigation