Abstract
In this paper, we consider the problem of analyzing dataflow programs with the property that actor production and consumption rates are not constant and fixed, but limited by intervals. Such interval ranges may result from uncertainty in the specification of an actor or as a design freedom of the model. Major questions such as consistencyand buffer memory requirementsfor single-processor scheduleswill be analyzed here for such specifications for the first time. Also, metamodeling formulations of interval limited dataflow are discussed, with special emphasis on the application to cyclo-static dataflow modeling.
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Jürgen Teich received his masters degree (Dipl.-Ing.) in 1989 from the University of Kaiserslautern (with honours).
From 1989 to 1993, he was PhD student at the University of Saarland, Saarbrücken, Germany from where he received his PhD degree (summa cum laude). His PhD thesis entitled ‘A Compiler for Application-Specific Processor Arrays‘summarizes his work on techniques for mapping computation intensive algorithms onto dedicated VLSI processor arrays.
In 1994, Dr. Teich joined the DSP design group of Prof. E. A. Lee and D.G. Messerschmitt in the Department of Electrical Engineering and Computer Sciences (EECS) at UC Berkeley where he was working in the Ptolemy project (PostDoc).
From 1995 to 1998, he held a position at Institute of Computer Engineering and Communications Networks Laboratory (TIK) at ETH Zürich, Switzerland, finishing his Habilitation entitled ‘Synthesis and Optimization of Digital Hardware Software Systems’ in 1996.
From 1998 to 2002, he was full professor in the Electrical Engineering and Information Technology department of the University of Paderborn, holding a chair in Computer Engineering.
Since 2003, he is appointed full professor in the Computer Science Institute of the Friedrich-Alexander University Erlangen-Nuremberg holding a chair in Hardware-Software-Co-Design.
Dr. Teich has been a member of multiple program committees of well-known conferences and workshops. He is member of the IEEE and author of a textbook on Co-Design edited by Springer in 1997.His research interests are massive parallelism, embedded systems, Co-Design, and computer architecture.
Since 2004, Prof. Teich is also an elected reviewer for the German Science Foundation (DFG) for the area of Computer Architecture and Embedded Systems. Prof. Teich is involved in many interdisciplinary national basic research projects as well as industrial projects. He is supervising 19 PhD students currently.
Shuvra S. Bhattacharyyais an associate professor in the Department of Electrical and Computer Engineering and the Institute for Advanced Computer Studies (UMIACS) at the University of Maryland, College Park. He is also an affiliate associate professor in the Department of Computer Science. Dr. Bhattacharyya is coauthor or coeditor of four books and the author or coauthor of more than 100 refereed technical articles. His research interests include VLSI signal processing, embedded software, and hardware/software co-design. He received the B.S. degree from the University of Wisconsin at Madison, and the Ph.D. degree from the University of California at Berkeley. Dr. Bhattacharyya has held industrial positions as a Researcher at the Hitachi America Semiconductor Research Laboratory (San Jose, California), and as a Compiler Developer at Kuck & Associates (Champaign, Illinois).
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Teich, J., Bhattacharyya, S.S. Analysis of Dataflow Programs with Interval-limited Data-rates. J VLSI Sign Process Syst Sign Image Video Technol 43, 247–258 (2006). https://doi.org/10.1007/s11265-006-7274-2
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DOI: https://doi.org/10.1007/s11265-006-7274-2