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A Decimal Floating-Point Divider Using Newton–Raphson Iteration

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Abstract

Increasing chip densities and transistor counts provide more room for designers to add functionality for important application domains into future microprocessors. As a result of rapid growth in financial, commercial, and Internet-based applications, hardware support for decimal floating-point arithmetic is now being considered by various computer manufacturers and specifications for decimal floating-point arithmetic have been added to the draft revision of the IEEE-754 Standard for Floating-Point Arithmetic (IEEE P754). In this paper, we presents an efficient arithmetic algorithm and hardware design for decimal floating-point division. The design uses an efficient piecewise linear approximation, a modified Newton–Raphson iteration, a specialized rounding technique, and a simplified decimal incrementer and decrementer. Synthesis results show that a 64-bit (16-digit) implementation of the decimal divider, which is compliant with the current version of IEEE P754, has an estimated critical path delay of 0.69 ns (around 13 FO4 inverter delays) when implemented using LSI Logic’s 0.11 micron Gflx-P standard cell library.

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References

  1. M. H. Weik, “The ENIAC Story,” http://ftp.arl.mil/~mike/comphist/eniac-story.html, 1961.

  2. M. F. Cowlishaw, “Decimal Arithmetic FAQ: Part 1—General Questions,” Available at http://www2.hursley.ibm.com/decimal/decifaq1.htm, 2003.

  3. M. Blair, S. Obenski, and P. Bridickas, “Patriot Missile Defense—Software Problem Led to System Failure at Dhahran, Saudi Arabia,” http://www.fas.org/spp/starwars/gao/im92026.htm, 1992.

  4. W. Kahan, “How Futile are Mindless Assessments of Roundoff in Floating-point Computation?,” Available at http://www.cs.berkeley.edu/~wkahan/Mind1ess.pdf, 2004.

  5. European Commission, “The Introduction of the Euro and the Rounding of Currency Amounts,” http://europa.eu.int/comm/economy_finance/publications/euro_papers/200%1/eup22en.pdf, March 1998.

  6. A. Tsang and M. Olschanowsky, “A Study of Database 2 Customer Queries,” IBM Technical Report 03.413, April 1991.

  7. M. F. Cowlishaw, “Decimal Floating-point: Algorism for Computers,” in Proceedings of the 16th IEEE Symposium on Computer Arithmetic, June 2003, pp. 104–111.

  8. JTC1/SC22/WG4, “Proposed Revision of ISO 1989:1985 Information Technology—Programming Languages, Their Environments and System Software Intefaces—Programming Language COBOL,” Available at http://www.cobolstandard.info/wg4/wg4.html, Dec 2001.

  9. Sun Microsystem, “Java 2 Platform Standard Edition v1.3.1,” Available at http://java.sun.com/j2se/1.3/docs/api/, 2001.

  10. Microsoft Corporation, “Visual Basic Language and Run-time Reference,” Available at http://msdn.microsoft.com/library/default.asp?url=/library/en-us/csspec%/html/CSharpSpecStart.asp, 2002.

  11. IBM Corporation, “The decNumber Library.” http://www2.hursley.ibm.com/decimal/decnumber.html, 2004.

  12. Microsoft Corporation, “C# Language Specification,” Available at http://msdn.microsoft.com/library/default.asp?url=/library/en-us/csspec%/html/CSharpSpecStart.asp, 2002.

  13. 754 Working Group, “DRAFT IEEE Standard for Floating-point Arithmetic,” Available at http://754r.ucbtest.org/drafts/, April 2004.

  14. M. A. Erle, M. J. Schulte, and J. M. Linebarger, “Potential Speedup Using Decimal Floating-point Hardware,” in Conference Record of the Thirty-sixth Asilomar Conference on Signals, Systems and Computers, 2002, pp. 1073–1077, Nov.

  15. M. J. Schulte, M. Lindberg, and A. Laxminarain, “Performance Evaluation of Decimal Floating-point Arithmetic,” in IBM Austin Center for Advanced Studies Conference, February 2005.

  16. A. Parashar, S. Gurumurthi, and A. Sivasubramaniam, “A Complexity-effective Approach to ALU Bandwidth Enhancement for Instruction-level Temporal Redundancy,” in 31st Annual International Symposium on Computer Architecture, June 2004.

  17. J. Thompson, M. J. Schulte, and N. Karra, “A 64-bit Decimal Floating-point Adder,” in Proceedings of the IEEE Computer Society Annual Symposium on Lafayette, LA, VLSI, February 2004.

  18. M. A. Erle and M. J. Schulte, “Decimal Multiplication via Carry-save Addition,” in Proceedings of IEEE International Conference on Application-Specific Systems, Architectures, and Processors, June 2003, pp. 337–347.

  19. L.-K. Wang and M. J. Schulte, “Decimal Floating-point Division Using Newton–Raphson Iteration,” in Proceedings of IEEE International Conference on Application-specific System, Architectures and Processors, September 2004, pp. 84–95.

  20. P. Soderquist and M. Leeser, “Area and Performance Tradeoffs in Floating-point Divide and Square-root Implementations,” ACM Comput. Surv., vol. 28, no. 3, 1996, pp. 518–564.

    Article  Google Scholar 

  21. M. J. Flynn and S. F. Oberman, Advanced Computer Arithmetic Design, Wiley, 2001.

  22. Yabe et al., Binary Coded Decimal Number Division Apparatus, U.S. Patent 4,634,220, January 1987.

  23. Yamaoka et al., Coded Decimal Non-restoring Divider, U.S. Patent 4,692,891, September 1987.

  24. F. Y. Busaba et al., “The IBM z900 Decimal Arithmetic Unit,” in Proceedings of the 35th Asilomar Conference on Signals, Systems and Computers, IEEE Computer Society, vol. 2, November 2001, pp. 1335–1339.

  25. C. F. Webb et al., Specialized Millicode Instructions for Packed Decimal Division, U. S. Patent 6,067,617, May 2000.

  26. D. E. Ferguson, Non-heuristic Decimal Divide Method and Apparatus, U.S. Patent 5,587,940, December 1996.

  27. M. F. Cowlishaw, “Densely Packed Decimal Encoding,” in IEE Proc., Comput. Digit. Tech., vol. 149, May 2002, pp. 102–104.

    Article  Google Scholar 

  28. N. Takagi, “Powering by a Table Look-up and a Multiplication with Operand Modification,” IEEE Trans. Comput., vol. 47, no. 4, 1998, pp. 1216–1222.

    Article  MathSciNet  Google Scholar 

  29. S. F. Oberman and M. J. Flynn, “Division Algorithms and Implementations,” IEEE Trans. Comput., vol. 46, no. 8, 1997, pp. 833–854.

    Article  MathSciNet  Google Scholar 

  30. S. F. Oberman and M. J. Flynn, “An Analysis of Division Algorithms and Implementations,” Technical Report, Stanford University, 1995.

  31. E. M. Schwarz, “Rounding for Quadratically Converging Algorithms for Division and Square Root,” in Proceedings of the 29th Asilomar Conference on Signals, Systems and Computers, IEEE Computer Society, 1995, pp. 600–603.

  32. S. F. Oberman, Design Issues in High Performance Floating Point Arithmetic Units, PhD thesis, Stanford University, Stanford, CA, 1996.

  33. V. G. Oklobdzija, “An Algorithmc and Novel Design of a Leading Zero Detector Circuit: Comparison with Logic Synthesis,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 2, March 1994, pp. 124–128.

    Article  Google Scholar 

  34. LSI Logic, “Gflx-p 0.11 micron SoC Technology,” Available at http://www.lsilogic.com/files/docs/marketing_docs/asic/gflx_pb.pdf, 2005.

  35. J. M. Tendler, J. S. Dodson, J. S. Fields Jr., H. Le, and B. Sinharoy, “POWER4 System Microarchitecture,” IBM J. Res. Develop., vol. 46, no. 1, 2002, pp. 5–26.

    Article  Google Scholar 

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Authors and Affiliations

  1. Department of ECE, University of Wisconsin-Madison, Madison, WI, USA

    Liang-Kai Wang & Michael J. Schulte

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  1. Liang-Kai Wang
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  2. Michael J. Schulte
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Correspondence to Liang-Kai Wang.

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Wang, LK., Schulte, M.J. A Decimal Floating-Point Divider Using Newton–Raphson Iteration. J VLSI Sign Process Syst Sign Im 49, 3–18 (2007). https://doi.org/10.1007/s11265-007-0058-5

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  • DOI: https://doi.org/10.1007/s11265-007-0058-5

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