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Configurable Data Memory for Multimedia Processing

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Abstract

In modern multimedia applications, memory bottleneck can be alleviated with special stride data accesses. Data elements in stride access can be retrieved in parallel with parallel memories, in which the idea is to increase memory bandwidth with several memory modules working in parallel and feed the processor with only necessary data. Arbitrary stride access capability with interleaved memories is described in previous research where the skewing scheme is changed at run time according to the currently used stride. This paper presents the improved schemes which are adapted to parallel memories. The proposed novel parallel memory implementation allows conflict free accesses with all the constant strides which has not been possible in prior application specific parallel memories. Moreover, the possible access locations are unrestricted and the accessed data element count equals to the number of memory modules. Timing and area estimates are given for Altera Stratix FPGA and 0.18 micrometer CMOS process with memory module count from 2 to 32. The FPGA results show 129 MHz clock frequency for a system with 16 memory modules when read and write latencies are 3 and 2 clock cycles, respectively. The complexity of the proposed system is shown to be a trade-off between application specific and highly configurable parallel memory system.

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  1. Institute of Digital and Computer Systems, Tampere University of Technology, Tampere, Finland

    Eero Aho, Jarno Vanne & Timo D. HÄmÄlÄinen

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  1. Eero Aho
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Aho, E., Vanne, J. & HÄmÄlÄinen, T.D. Configurable Data Memory for Multimedia Processing. J Sign Process Syst Sign Image 50, 231–249 (2008). https://doi.org/10.1007/s11265-007-0126-x

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  • DOI: https://doi.org/10.1007/s11265-007-0126-x

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