Skip to main content
Log in

A Mapping Framework Based on Packing for Design Space Exploration of Heterogeneous MPSoCs

  • Published:
Journal of Signal Processing Systems Aims and scope Submit manuscript

Abstract

The computational demand of signal processing algorithms is rising continuously. Heterogeneous embedded multiprocessor systems-on-chips are one solution to satisfy this demand. But to be able to take advantage of these systems, new strategies are required to map applications to such a system and to evaluate the systems performance at a very early design stage. We will present a framework for static, analytical, bottom-up temporal and spatial mapping of applications to MPSoCs based on packing. This mapping framework allows easy performance evaluation and design space exploration of heterogeneous systems on chip.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7

Similar content being viewed by others

References

  1. Blume, H., Feldkämper, H. T., & Noll, T. G. (2005). Model-based exploration of the design space for heterogeneous systems on chip. Journal of VLSI Signal Processing Systems, 40(1), 19–34.

    Article  Google Scholar 

  2. Kienhuis, B., Deprettere, E., Vissers, K., & van der Wolf, P. (1997). An approach for quantitative analysis of application-specific dataflow architectures. In Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP’97) (pp. 338–349).

  3. Pimentel, A. D., Erbas, C., & Polstra, S. (2006). A systematic approach to exploring embedded system architectures at multiple abstraction levels. IEEE Transactions on Computers, 55(2), 99–112.

    Article  Google Scholar 

  4. Lee, E. A. (2003). Overview of the Ptolemy project. Technical memorandum UCB/ERL M03/25, University of California, Berkeley, CA, 94720, USA.

  5. Reyes, V., Kruijtzer, W., Bautista, T., Alkadi, G., & Nunez, A. (2006). A unified system-level modeling and simulation environment for MPSoC design: MPEG-4 decoder case study. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’06) (pp. 474–479).

  6. Bakshi, A., Prasanna, V. K., & Ledeczi, A. (2001). MILAN: A model based integrated simulation framework for design of embedded systems. In Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems (LCTES’01) (pp. 82–93).

  7. Erbas, C., Erbas, S. C., & Pimentel, A. D. (2003). A multiobjective optimization model for exploring multiprocessor mappings of process networks. In Proceedings of the IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS’03) (pp. 182–187).

  8. Bellens, P., Perez, J. M., Badia, R. M., & Labarta, J. (2006). CellSs: A programming model for the Cell BE architecture. In Proceedings of the ACM/IEEE Conference on Supercomputing (SC’06) (pp. 86–96).

  9. Coffland, J. E., & Pimentel, A. D. (2003). A software framework for efficient system-level performance evaluation of embedded systems. In M. Matsui, R. J. Zuccherato (Eds.), SAC 2003, LNCS, vol. 4006 (pp. 666–671). New York: Springer.

    Google Scholar 

  10. Turjan, A., Kienhuis, B., & Deprettere, E. (2004). Translating affine nested-loop programs to process networks. In Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES’04) (pp. 220–229).

  11. Cichon, G., & Fettweis, G. (2003). MOUSE: A shortcut from matlab source to SIMD DSP assembly code. In Proceedings of the International Workshop on Systems, Architectures, MOdeling, and Simulation (SAMOS’03) (pp. 159–167)

  12. Cytron, R., Ferrante, J., Rosen, B. K., Wegman, M. N., & Zadeck, F. K. (1991). Efficiently computing static single assignment form and the control dependence graph. ACM Transactions on Programming Languages and Systems, 13(4), 451–490.

    Article  Google Scholar 

  13. Dijkstra, E. W. (1959). A note on two problems in connexion with graphs. Numerische Mathematik, 1(1), 269–271.

    Article  MATH  MathSciNet  Google Scholar 

  14. Liu, C. L., & Layland, J. W. (1973). Scheduling algorithms for multiprogramming in a hard-real-time environment. Journal of the Association for Computing Machinery, 20(1), 46–61.

    MATH  MathSciNet  Google Scholar 

  15. Chaitin, G. J., Auslander, M. A., Chandra, A. K., Cocke, J., Hopkins, M. E., & Markstein, P. W. (1981). Register allocation via coloring. Computer Languages, 6(1), 47–57.

    Article  Google Scholar 

  16. Belov, G., Chiglintsev, A. V., Filippova, A. S., Mukhacheva, E., Scheithauer, G., & Shirgazin, R. (2005). The two-dimensional strip packing problem: A numerical experiment with waste-free instances using algorithms with block structure. MATH-NM-01-2005, TU Dresden (preprint).

  17. Ristau, B., & Fettweis, G. (2006). An optimization methodology for memory allocation and task scheduling in SoCs via linear programming. In S. Vassiliadis, S. Wong, & T. Hämäläinen (Eds.), SAMOS 2006, LNCS, vol. 4017 (pp. 89–98). New York: Springer.

    Google Scholar 

  18. Matus, E., Seidel, H., Limberg, T., Robelly, P., & Fettweis, G. (2006). A GFLOPS vector-DSP for broadband wireless applications. In Proceedings of the IEEE Custom Integrated Circuits Conference (CICC’06) (pp. 543–546).

  19. Cichon, G., Robelly, P., Seidel, H., Matus, E., Bronzel, M., & Fettweis, G. (2004). Synchronous transfer architecture (STA). In A. Pimentel, & S. Vassiliadis (Eds.), SAMOS IV, LNCS, vol. 3133 (pp. 343–352). New York: Springer.

    Google Scholar 

  20. Linderoth, J. T., & Ralphs, T. K. (2005). Noncommercial software for mixed-integer linear programming. In J. Karlof (Ed.), Integer Programming: Theory and Practice. Sheffield: CRC.

    Google Scholar 

Download references

Acknowledgements

This research is supported by NXP Semiconductors Dresden within the project MxMobile Multi-Standard Mobile Platform of the German Federal Ministry of Education and Research.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Bastian Ristau.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Ristau, B., Limberg, T. & Fettweis, G. A Mapping Framework Based on Packing for Design Space Exploration of Heterogeneous MPSoCs. J Sign Process Syst Sign Image Video Technol 57, 45–56 (2009). https://doi.org/10.1007/s11265-008-0171-0

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11265-008-0171-0

Keywords

Navigation