Skip to main content
Log in

SPOCS: Application Specific Signal Processor for OFDM Communication Systems

  • Published:
Journal of Signal Processing Systems Aims and scope Submit manuscript

Abstract

This paper presents an Application-Specific Signal Processor (ASSP) for Orthogonal Frequency Division Multiplexing (OFDM) Communication Systems, called SPOCS. The instruction set and its architecture are specially designed for OFDM systems, such as Fast Fourier Transform (FFT), scrambling/descrambling, puncturing, convolutional encoding, interleaving/deinterleaving, etc. SPOCS employs the optimized Data Processing Unit (DPU) to support the proposed instructions and the FFT Address Generation Unit (FAGU) to automatically calculate input/output data addresses. In addition, the proposed Bit Manipulation Unit (BMU) supports efficient bit manipulation operations. SPOCS has been synthesized using the SEC 0.18 μm standard cell library and has a much smaller area than commercial DSP chips. SPOCS can reduce the number of clock cycles over 8%~53% for FFT and about 48%~84% for scrambling, convolutional encoding and interleaving compared with existing DSP chips. SPOCS can support various OFDM communication standards, such as Wireless Local Area Network (WLAN), Digital Audio Broadcasting (DAB), Digital Video Broadcasting-Terrestrial (DVB-T), etc.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16

Similar content being viewed by others

References

  1. Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications, IEEE Std 802. 11a-1000, Sept.

  2. Digital Video Broadcasting (DVB); Framing structure, channel coding and modulation for digital terrestrial television, ETSI EN 300 744 v1.4.1, Jan.

  3. Kumura, T., Ishii, D., Ikekawa, M., Kuroda, I., & Yoshida, M. (2001). A low-power programmable DSP core architecture for 3G mobile terminals. In Proc. 2001 IEEE Int. Conf. on Signal Processing Applications and Technology, vol. 2 (pp. 1017–1020), May.

  4. Glossner, J., Moreno, J., Moudgill, M., Derby, J., Hokenek, E., Meltzer, D., Shavadron, U., & Ware, M. (2000). Trends in compilable DSP architecture. In Proc. IEEE Workshop on Signal Processing Syst. (pp. 181–199).

  5. Jo, B. G., & Sunwoo, M. H. (2005). New Continuous Flow Mixed-Rasix (CFMR) FFT Processor. IEEE Transactions on Circuits and Systems I, 52, 281–284.

    MathSciNet  Google Scholar 

  6. He, S., & Torkelson, M. (1998). Design and implementation of a 1024-point pipeline FFT processor. In Proc. IEEE Custom Integrated Circuits Conference (pp. 131–134).

  7. Baas, B. M. (1992). A low-power, high-performance, 1024-point FFT processor. IEEE Journal of Solid-State Circuits Systems II, 39, 312–316.

    Google Scholar 

  8. Hidalgo, J. A., Lopez, J., Aruguello, F., & Zapata, E. L. (1999). Area-efficient architecture for fast Fourier transform. IEEE Transactions on Circuits Systems II, 46, 187–193.

    Article  Google Scholar 

  9. Forward Concepts (2004). DSP market bulletin, Apr.

  10. ADSP-2016 SHARC DSP reference. Norwood, MA: Analog Device, Inc.

  11. SandBridge’s SandBlaster DSP and Tensilica’s FLIX. Retrieved from http://www.sandbridgetech. com.

  12. Multichannel digital audio processor with DDXä, ST Microelectronics.

  13. Chen, C. K., Tseng, P. C., Chang, Y. C., & Chen, L. G. (2001). A digital signal processor with programmable correlator array architecture for third generation wireless communication system. IEEE Transactions on Cicuits Systems II, 48, 1110–1120.

    Article  MATH  Google Scholar 

  14. Kim, B.-W., Yang, J.-H., Hwang, C.-S., Kwon, Y.-S., Lee, K.-M., Kim, I.-H., et al. (1999). MDSP-II: a 16-bit DSP with mobile communication accelerator. IEEE Journal of Solid-State Circuits, 34, 397–404.

    Article  Google Scholar 

  15. Kolagotla, R. K., Fridman, J., et al. (2002) High performance dual-MAC DSP architecture. IEEE Signal Processing Magazine, 42–53, July.

  16. Liu, Z., Dickson, K., & McCanny, J. V. (2005). Application-specific instruction set processor for SoC implementation of modern signal processing algorithms. IEEE Transactions on Circuits Systems I, 52, 755–765.

    Article  Google Scholar 

  17. Kneip, J., Weiss, M., Drescher, W., Aue, V., Strobel, J., Oberthur, T., et al. (2002). Single chip programmable baseband ASSP for 5 GHz wireless LAN applications. IEICE Transactions on Electronics, E85-C, 359–367.

    Google Scholar 

  18. Nava, M. D., & Okvist, G. S. (2002) The Zipper prototype: a complete and flexible VDSL multicarrier solution. IEEE Communications Magazine, 92–105, Dec.

  19. Frescura, F., Pielmeier, S., Reali, G., Baruffa, G., & Cacopardi, S. (1999). DSP Based OFDM demodulator and equalizer for professional DVB-T teceivers. IEEE Transactions on Broadcasting, 45, 323–332.

    Article  Google Scholar 

  20. Lee, J. H., Heo, K. L., Sunwoo, M. H., & Oh, S. K. (2005). Implementation of application-sepcific DSP for OFDM systems. In Proceedings of the IEEE International Symposium on Circuits and Systems, May.

  21. Kim, S. D., Jeong, S. H., Sunwoo, M. H., & Kim, K. H. (2005). Novel bit manipulation unit for communication digital signal processors. In Proceedings of the IEEE International Symposium on Circuits and Systems, May.

  22. Kang, J. Y., Cho, S. M., & Sunwoo, M. H. FFT operation apparatus of programmable processors and operating method thereof. US Patent Pending.

  23. Kang, J. Y., Cho, S. M., & Sunwoo, M. H. FFT operating apparatus of programmable processors and operation method thereof. European Patent Pending.

  24. Jung, S. H., & Sunwoo, M. H. Bit manipulation operation circuit and method in programmable processor. US Patent Pending.

  25. Motorola, Inc. (1993). Implementation of fast fourier transforms on Motorola’s digital signal processors.

  26. Infineon Technology, Inc. Optimal FFT Implementation on the Carmelä DSP Core.

  27. Roy, E., & Crawford, D. H. (2000) Programming techniques for parallel DSP architectures: optimal performance on the StarCore SC140. In Proc ICSPAT 2000.

  28. Motorola, Inc. (1966). DSP56600 16-bit digital signal processor family manual.

  29. Infineon Technology, Inc. (2000). Carmelä DSP product overview.

  30. SC140 functional libraries, Motorola Inc. Retrieved from http://www.motorola.com

  31. TMS320C62xx iser’s manual. Dallas, TX: Texas Instruments Inc.

  32. Tiwari, V., Malik, S., & Wolfe, A. (1994). Power analysis of embedded software: a first step towards software power minimization. IEEE Transactions on VLSI Systems, 2, 506–526.

    Article  Google Scholar 

  33. Radio broadcasting systems; Digital Audio Broadcasting (DAB) to mobile, portable and fixed receivers, ETSI 300 401, 2nd edition, May.

  34. VDSL Alliance (1999). VDSL alliance draft standard proposal, April.

  35. HomePlug Powerline Alliance (2000). HomePlug 0.5 Draft Medium Interface Specification, Nov.

  36. Sereni, E., Culicchi, S., Vinit, V., Luchetti, E., Ottaviani, S., & Salvi, M. (2001) A software RADIO OFDM transceiver for WLAN applications. Electronic and Information Engineering Department, University of Perugia, Italy.

  37. Pandey, A., Agrawalla, S. R., & Manivannan, S. (2006). VLSI implementation of OFDM modem. WIPRO Ltd.

  38. Texas Instruments Inc. (2002) TMS320C62x/C67x Power Consumption Summary, July.

Download references

Acknowledgement

This work was supported in part by IT R&D Project funded by Korean Ministry of Information and Communications, in part by the second stage of Brain Korea 21 Project in 2006, and in part by IDEC (IC Design Education Center).

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Myung H. Sunwoo.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Baek, J.H., Kim, S.D. & Sunwoo, M.H. SPOCS: Application Specific Signal Processor for OFDM Communication Systems. J Sign Process Syst Sign Image Video Technol 53, 383–397 (2008). https://doi.org/10.1007/s11265-008-0240-4

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11265-008-0240-4

Keywords

Navigation