Skip to main content
Log in

Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems

  • Published:
Journal of Signal Processing Systems Aims and scope Submit manuscript

Abstract

This paper shows that when a digital receiver is designed utilizing two clock scopes, the digital down-converter can be designed to be efficient in terms of area and power consumption. The main design parameter that contributes to make the design efficient is the relationship between the transition band of the designed filter and its sampling frequency.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Figure 1
Figure 2
Figure 3
Figure 4

Similar content being viewed by others

References

  1. European Telecommunications Standards Institute (1997). Digital Video Broadcasting (DVB), European standard (Telecommunications series), EN 300 421V1.1.2.

  2. Cardells-Tormo, F., Pérez-Pascual, A., Torres-Carot, V., Valls-Coquillat, J., & Almenar-Terré, V. (2003). Design of a DVB-S Receiver in FPGA. In IEEE Workshop on Signal Processing Systems, SiPS.

  3. Meyr, H., Moeneclaey, M., & Fechtel, S. A. (1998). Digital communications receivers. Synchronization, channel estimation and signal processing (Vol. 2). New York: Wiley.

    Book  Google Scholar 

  4. Gardner, F. M. (1993). Interpolation in digital modems—Part I: Fundamentals. IEEE Transactions on Communications, 41, 501–507.

    Article  MATH  Google Scholar 

  5. Cardells, F., Valls, J., Almenar, V., Torres, V. (2002). Efficient FPGA-based QPSK Demodulation Loops: Application to the DVB standard. In 12th International Conference on Field Programmable Logic and Applications, FPL’2002. Sept. Montpellier, France.

  6. Vaughan, R. G. (1991). The theory of bandpass sampling. IEEE Transactions on Signal Processing, 39(9), 1973–1984.

    Article  Google Scholar 

  7. Parhi, K. K. (1999). VLSI signal processing system. New York: Wiley.

    Google Scholar 

Download references

Acknowledgements

This research was supported by FEDER, the Spanish Ministerio de Educación y Ciencia, under Grant no. TEC2005-08406-C03-01 and Generatitat Valenciana, under Grant no. GV06/114.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to A. Pérez-Pascual.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Pérez-Pascual, A., Sansaloni, T., Torres, V. et al. Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems. J Sign Process Syst Sign Image Video Technol 56, 35–40 (2009). https://doi.org/10.1007/s11265-008-0254-y

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11265-008-0254-y

Keywords

Navigation