Skip to main content
Log in

Tracking Forecast Memories for Stochastic Decoding

  • Published:
Journal of Signal Processing Systems Aims and scope Submit manuscript

Abstract

This paper proposes Tracking Forecast Memories (TFMs) as a novel method for implementing re-randomization and de-correlation of stochastic bit streams in stochastic channel decoders. We show that TFMs are able to achieve decoding performance similar to that of the previous re-randomization methods in the literature (i.e., edge memories), but they exhibit much lower hardware complexity. We then present circuit topologies for analog implementation of TFMs.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14

Similar content being viewed by others

Notes

  1. It should noted that the amount of reduction of physical wires between PNs and VNs in stochastic decoding is similar to other bit-serial decoding approaches such as the bit-serial MSA. This reduction directly translates to a high logic utilization of the decoder. For example, an 86% per-area core logic utilization was reported in [7] using the bit-serial MSA. This logic utilization is much higher than the 50% logic utilization obtained in [6] using 4-bit SPA.

References

  1. DVB (2003). The digital video broadcasting standard. www.dvb.org.

  2. The IEEE 802.11n Working Group (2009). IEEE 802.11 wireless local area networks. www.ieee802.org/11/.

  3. The IEEE 802.16 Working Group (2009). The IEEE 802.16 working Group on broadband wireless access standards. www.ieee802.org/16/.

  4. The IEEE P802.3an 10GBASE-T Task Force (2006). The IEEE P802.3an 10GBASE-T Task Force homepage. www.ieee802.org/3/an

  5. Amat, A., Benedetto, S., Montorsi, G., Vogrig, D., Neviani, A., & Gerosa, A. (2006). Design, simulation, and testing of a CMOS analog decoder for the block length-40 UMTS turbo code. IEEE Transactions on Communications, 54(11), 1973–1982. doi:10.1109/TCOMM.2006.884836.

    Article  Google Scholar 

  6. Blanksby, A., & Howland, C. (2002). A 690-mw 1-Gb/s 1024-b rate-1/2 low-density parity-check code decoder. IEEE Journal of Solid-State Circuits, 37(3), 404–412.

    Article  Google Scholar 

  7. Brandon, T. L., Hang, R., Block, G., Gaudet, V., Cockburn, B. F., Howard, S. L., et al. (2008). A scalable LDPC decoder ASIC architecture with bit-serial message exchange. Integration, the VLSI Journal, 41(3), 385–398.

    Article  Google Scholar 

  8. Darabiha, A., Carusone, A. C., & Kschischang, F. R. (2008). Block-interlaced LDPC decoders with reduced interconnect complexity. IEEE Transactions on Circuits and Systems-II: Express Briefs, 55(1), 74–78.

    Article  Google Scholar 

  9. Darabiha, A., Carusone, A. C., & Kschischang, F. R. (2007). A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-um CMOS. In Custom integrated circuits Conf. (pp. 459–462), U.S.A.

  10. Gaudet, V., & Rapley, A. (2003). Iterative decoding using stochastic computation. Electronics Letters, 39(3), 299–301.

    Article  Google Scholar 

  11. Gross, W. J., Gaudet, V., & Milner, A. (2005). Stochastic implementation of LDPC decoders. In The 39th Asilomar conf. on signals, systems, and computers (pp. 713–717). Pacific Grove, CA.

    Google Scholar 

  12. Hemati, S., Banihashemi, A., & Plett, C. (2006). A 0.18μm analog min-sum iterative decoder for a (32,8) low-density parity-check (LDPC) code. IEEE Journal of Solid-State Circuits, 41(11), 2531–2540.

    Article  Google Scholar 

  13. Kschischang, F., Frey, B., & Loeliger, H. (2001). Factor graphs and the sum-product algorithm. IEEE Transactions on Information Theory, 47(2), 498–519.

    Article  MATH  MathSciNet  Google Scholar 

  14. MacKay, D. J. C., & Neal, R. M. (1996). Near Shannon limit performance of low density parity check codes. Electronics Letters, 32(18), 1645–1646.

    Article  Google Scholar 

  15. Mannor, S., Shamma, J. S., & Arslan, G. (2007). Online calibrated forecasts: Memory efficiency versus universality for learning in games. Machine Learning, 67(1–2), 77–115. doi:10.1007/s10994-006-0219-y.

    Article  Google Scholar 

  16. Ortega, J. M., & Rheinboldt, W. C. (1970). Iterative solution of nonlinear equations in several variables. New York: Academic.

    MATH  Google Scholar 

  17. Rapley, A., Winstead, C., Gaudet, V., & Schlegel, C. (2003). Stochastic iterative decoding on factor graphs. In Proc. of the 3rd int. symp. on turbo codes and related topics (pp. 507–510). Brest, France.

    Google Scholar 

  18. Sarkis, G., Mannor, S., & Gross, W. (2009). Stochastic decoding of LDPC codes over GF(q). In ICC 2009 symposium on selected areas in communications. Dresden, Germany.

    Google Scholar 

  19. Sharifi Tehrani, S., Gross, W. J., & Mannor, S. (2006). Stochastic decoding of LDPC codes. IEEE Communication Letters, 10(10), 716–718.

    Article  Google Scholar 

  20. Sharifi Tehrani, S., Jego, C., Zhu, B., & Gross, W. J. (2008) Stohastic decoding of linear block codes with high-densiy parity-check matrices. IEEE Transactions on Signal Processing, 56(11), 5733–5739.

    Article  MathSciNet  Google Scholar 

  21. Sharifi Tehrani, S., Mannor, S., & Gross, W. J. (2008). Fully parallel stochastic LDPC decoders. IEEE Transactions on Signal Processing, 56(11), 5692–5703.

    Article  MathSciNet  Google Scholar 

  22. Sharifi Tehrani, S., Mannor, S., & Gross, W. J. (2007). An area-efficient FPGA-based architecture for fully-parallel stochastic LDPC decoding. In Proc. of the IEEE workshop on signal processing systems (SiPS) (pp. 255–260). Shanghai, China

    Chapter  Google Scholar 

  23. Sharifi Tehrani, S., Naderi, A., Kamendje, G., Mannor, S., & Gross, W. J. (2009). Tracking forecast memories in stochastic decoders. In IEEE international conference on acoustics, speech and signal processing (pp. 561–564). Taipei, Taiwan

    Chapter  Google Scholar 

  24. Winstead, C. (2005). Error-control decoders and probabilistic computation. In Tohoku Univ. 3rd SOIM-COE conf. (pp. 349–352). Sendai, Japan.

    Google Scholar 

  25. Winstead, C., Gaudet, V., Rapley, A., & Schlegel, C. (2005). Stochastic iterative decoders. In IEEE ISIT (pp. 1116–1120).

  26. Winstead, C., Nguyen, N., Gaudet, V., & Schlegel, C. (2006). Low-voltage CMOS circuits for analog iterative decoders. IEEE Transactions on Circuits and Systems I: Regular Papers, 53(4), 829–841. doi:10.1109/TCSI.2005.859773.

    Article  Google Scholar 

  27. Yang, S., Li, X., Wang, Y., & Qiu, Y. (2008). A two-level pipeline input interface circuit with probability splitting computation function used in analog decoder. In Proc. of the 9th international conference on solid-state and integrated-circuit technology (ICSICT) (pp. 1807–1810). doi:10.1109/ICSICT.2008.4734907.

Download references

Acknowledgements

We would like to acknowledge the Natural Sciences and Engineering Research Council of Canada (NSERC), the Canada Research Chairs (CRC), and the Fonds Québécois de la Recherche sur la Nature et les Technologies (FQRNT) for their financial support.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Warren J. Gross.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Sharifi Tehrani, S., Naderi, A., Kamendje, GA. et al. Tracking Forecast Memories for Stochastic Decoding. J Sign Process Syst 63, 117–127 (2011). https://doi.org/10.1007/s11265-009-0441-5

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11265-009-0441-5

Keywords

Navigation