Skip to main content
SpringerLink
Log in

Hardware/Software Co-reconfigurable Instruction Decoder for Adaptive Multi-core DSP Architectures

  • Published:
Journal of Signal Processing Systems Aims and scope Submit manuscript

Abstract

A programmable instruction decoder (PID) is introduced for designing adaptive multi-core DSP architectures by using a hardware/software co-reconfigurable approach without employing programmable devices. This PID permits DSP software developers for post-manufacturing modification of their DSP instruction sets to add their application-specific instructions whenever necessary. In addition, PID offers software developers an enhanced means to utilize the underlying DSP architectures by rescheduling implemented micro-operations for their tailored instructions in the DSP processors. Thus, emerging DSP applications can be swiftly and efficiently re-imported to PID-based DSP processors without re-fabrication of new DSP chips. In addition to instruction-level modification, an innovative instruction-packing procedure for PID is presented for further enhancement of the PID-based DSP systems. PID architecture was developed and implemented in VHDL. The PID-based DSP systems were also developed and evaluated to demonstrate various post-manufacturing adaptabilities in DSP processor systems. Various multi-core DSP architectures based on Texas Instruments’ TMS320C55 DSP processor were used for evaluating performance and adaptability of this new programmable instruction decoder.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7

Similar content being viewed by others

References

  1. Jerraya, A., Tenhunen, H., & Wolf, W. (2005). Multiprocessor systems-on-chips. IEEE Computer, 38(7), 36–40.

    Google Scholar 

  2. Jerraya, A., Petrot, F., & Bouchhima, A. (2006). Programming models and HW-SW interfaces abstraction for multi-processor SoC. IEEE Design automation conference, July 2006, pp. 280–285.

  3. Martin, G. (2006). Overview of the MPSoC design challenge. IEEE Design automation conference, July 2006, pp. 274–279.

  4. Zhaohui, L., Dickson, K., & McCanny, J. (2005). Application-specific instruction set processor for SoC implementation of modern signal processing algorithms. IEEE Transactions on Circuits and Systems, 52(4), 755–765.

    Article  Google Scholar 

  5. Leibson, S., & Kim, J. (2005). Configurable processors: a new era in chip design. IEEE Computer, 38(7), 51–59.

    Google Scholar 

  6. Zhaohui, L., Dickson, K., & McCanny, J. (2005). Application-specific instruction set processor for SoC implementation of modern signal processing algorithms. IEEE Transactions on Circuits and Systems, April 2005, pp. 755–765.

  7. Barat, F., Lauwereins, R., & Deconinck, G. (2002). Reconfigurable instruction set processors from a hardware/software perspective. IEEE Transactions on Software Engineering, 28(9), 847–862.

    Article  Google Scholar 

  8. Borgatti, M., Lertora, F., et al. (2003). A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA, and customizable I/O. IEEE Journal of Solid-State Circuits, 38(3), 521–529.

    Article  Google Scholar 

  9. Atasu, K., Pozzi, L., & Ienne, P. (2003). Automatic application-specific instruction-set extensions under microarchitectural constraints. In Proc. of IEEE Design Automation Conference, June 2003, pp. 256–261.

  10. Mesman, B., Zhao, Q. et al. (2003). Reconfigurable instruction-set application-tuning for DSP. Journal of Circuits, Systems, and Computers, June 2003, pp. 333–352.

  11. Qingfeng, Z., Bin, X., & Edwin, H. (2003). Code size reduction technique and implementation for software-pipelined DSP applications. ACM Transactions on Embedded Computing Systems, 2(4), 590–613.

    Article  Google Scholar 

  12. Hazelwood, K., & Smith, M. (2006). Managing bounded code caches in dynamic binary optimization systems. ACM Transactions on Architecture and Code Optimization, 3(3), 263–294.

    Article  Google Scholar 

  13. Pegatoquet, A., Gresset, E. et al. (1999). Rapid development of optimzed DSP code from a high level description through software estimation. ACM/IEEE Design Automation Conference.

  14. Scott, K., Kumar, N., Velusamy, S., Childers, B., Davidson, J., & Soffa, M. L. (2003). Retargetable and reconfigurable software dynamic translation. International Symposium on Code Generation and Optimization, March 2003, pp.36–37.

  15. Dehnert, J., Grant, B. K. et al. (2003). The Transmeta code morphing software: using speculation, recovery, and adaptive retranslation to address real-life challenges. International Symposium on Code Generation and Optimization, pp. 15–24.

  16. Jung, Y. (2006). Design and optimization of a programmable instruction decoder for DSP architecture. IEEE Signal Processing Systems, Oct. 2006, pp. 354–359.

  17. DeHon, A. (1996). DPGA Utilization and Application. ACM International Symposium on Field Programmable Gate Arrays, pp. 115–121.

  18. Abramovici, M., Bradley, P., Dwarakanath, K., Levin, P., Memmi, G., & Miller, D. (2006). Programming models and HW-SW interfaces abstraction for multi-processor SoC. IEEE Design automation conference, July 2006, pp. 7–12.

  19. Jung, Y. (2006). Hardware/software co-reconfigurable multimedia architecture. IEEE Workshop on Embedded Systems for Real-time Multimedia, Oct. 2006, pp. 73–78.

  20. DeHon, A. & Wawrzynek, J. (1999). Reconfigurable computing: what, why, and implications for design automation. IEEE/ACM Design Automation Conference, 1999, pp. 610–615.

  21. Hartenstein, R. (2005). Handbook of nature-inspired and innovative computing. Integrating Classical Models with Emerging Technologies, Springer.

  22. Lysaght, P., & Subrahmanyam, P. (2005). Advances in configurable computing. IEEE Design and Test of Computers, 22(2), 85–89.

    Article  Google Scholar 

  23. Moore, G. (1965). Cramming more components onto integrated circuits. Electronics, 38(8).

  24. Becker, J., & Hartenstein, R. (2003). Configware and morphware going mainstream. Journal of Systems Architecture, 49(4–6), 127–142.

    Article  Google Scholar 

  25. Vanne, J., Aho, E., Hämäläinen, T., & Kuusilinna, K. (2006). A high-performance sum of absolute difference implementation for motion estimation. IEEE Transactions on Circuits and Systems for Video Technology, 16(7), 876–883.

    Article  Google Scholar 

  26. Texas Instruments, TMS320C55x DSP Mnemonic Instruction Set Reference Guide, Oct. 2002.

  27. ARM, ARM® Instruction Set, Oct. 2003.

  28. Texas Instruments, TMS320C55x DSP Algebraic Instruction Set Reference Guide, Oct. 2002.

  29. Altera Corp., Stratix II Device Handbook, Feb. 2004.

  30. Altera Corp., Stratix III Device Family–The Lowest Power High-Performance FPGAs, 2007.

  31. Jung, Y. (2007). Fault-recovery non-FPGA-based adaptable computing system design. IEEE NASA/ESA Conference on Adaptive Hardware and Systems, pp. 709–716.

  32. Jung, Y. (2008). Non-FPGA-based field-programmable self-repairable (FPSR) microarchitecture. IEEE NASA/ESA Conference on Adaptive Hardware and Systems, pp. 93–100.

  33. Shee, S. & Parameswaran, S. (2007). Design methodology for pipelined heterogeneous multiprocessor system. ACM/IEEE Design Automation Conference, pp. 811–816.

Download references

Author information

Authors and Affiliations

  1. Electrical and Computer Engineering, Gannon University, 109 University Square, Erie, PA, USA

    Yong-Kyu Jung

Authors
  1. Yong-Kyu Jung
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Yong-Kyu Jung.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Jung, YK. Hardware/Software Co-reconfigurable Instruction Decoder for Adaptive Multi-core DSP Architectures. J Sign Process Syst 62, 273–285 (2011). https://doi.org/10.1007/s11265-010-0461-1

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11265-010-0461-1

Keywords

Search

Navigation