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Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis

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Abstract

Multimedia applications such as video and image processing are often characterized as computation intensive applications. For these applications the word-length of data and instructions is different throughout the application. Generating hardware architectures is not a straightforward task since it requires a deep word-length analysis in order to properly determine what hardware resources are needed. In this paper we suggest an automated design methodology based on high-level synthesis which takes care of data word-length and interconnection resource cost in order to generate area and power efficient fixed-point architectures for DSP applications. Both ASIC and FPGA technologies are targeted. Experimental results show that our proposed approach reduces area by 6% to 42% on FPGA technology and by 9% to 48 % on ASIC compared to previous approaches. Power saving can reach up to 44% on FPGA technology and 36% on ASIC.

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Notes

  1. FPGA devices particularly

  2. http://www.enseirb.fr/∼legal/wp_graphlab

  3. At the hardware design level, when the width of a data is smaller than the resource’s one, a data expansion is required. The VHDL “resize” standard function (IEEE.NUMERIC_STD library) is used in practice to automate this data expansion during the hardware generation step of the design flow (Fig. 7).

  4. In that case, no re-scheduling is realized in order to obtain a solution in a short run-time. The set of resources is increased and the scheduling of the next operations benefits of this update.

  5. Because area is not always linear to the data-width (a multiplier for example, see Tables 1 and 2), we use polynomial models to compute resource area. These models come from our characterizations of the platforms we target.

  6. In practice, it also reduces the actual interconnection cost

  7. For comprehensive comparison of the resource usage, we enforce multipliers to be implemented using logic elements, not DSP blocks, with FPGA targets.

  8. depending on the values of coefficients Cu, Cv.

  9. Profiles 1, 2 and 3 respectively require (worst case) resources with 24, 32 and 26 bits when they are separately considered.

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Authors and Affiliations

  1. IMS Laboratory, CNRS - UMR 5218, Bordeaux Polytechnic Institute, University of Bordeaux, Talence, France

    Bertrand Le Gal

  2. French National Institute for Research in Computer Science and Control, INRIA/IRISA, Lannion, France

    Emmanuel Casseau

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  1. Bertrand Le Gal
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  2. Emmanuel Casseau
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Correspondence to Bertrand Le Gal.

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Le Gal, B., Casseau, E. Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis. J Sign Process Syst 62, 341–357 (2011). https://doi.org/10.1007/s11265-010-0467-8

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