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FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-sized Data

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Abstract

Applications based on Discrete Fourier Transforms (DFT) are extensively used in several areas of signal and digital image processing. Of particular interest is the two-dimensional (2D) DFT which is more computation- and bandwidth-intensive than the one-dimensional (1D) DFT. Traditionally, a 2D DFT is computed using Row-Column (RC) decomposition, where 1D DFTs are computed along the rows followed by 1D DFTs along the columns. Both application specific and reconfigurable hardware have utilized this scheme for high-performance implementations of 2D DFT. However, architectures based on RC decomposition are not efficient for large input size data due to memory bandwidth constraints. In this paper, we propose an efficient architecture to implement 2D DFT for large-sized input data based on a novel 2D decomposition algorithm. This architecture achieves very high throughput by exploiting the inherent parallelism due to the algorithm decomposition and by utilizing the row-wise burst access pattern of the external memory. A high throughput memory interface has been designed to enable maximum utilization of the memory bandwidth. In addition, an automatic system generator is provided for mapping this architecture onto a reconfigurable platform of Xilinx Virtex-5 devices. For a 2K ×2K input size, the proposed architecture is 1.96 times faster than RC decomposition based implementation under the same memory constraints, and also outperforms other existing implementations.

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Acknowledgements

This work is supported in part by a grant from DARPA W911NF-05-1-0248. In addition, the authors gratefully acknowledge the help of Dr. Nikos Pitsianis and Dr. Xiaobai Sun of Duke University.

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Authors and Affiliations

  1. School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ, USA

    Chi-Li Yu, Lanping Deng & Chaitali Chakrabarti

  2. Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA, USA

    Jung-Sub Kim, Srinidhi Kestur & Vijaykrishnan Narayanan

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  1. Chi-Li Yu
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  2. Jung-Sub Kim
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  3. Lanping Deng
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  4. Srinidhi Kestur
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  5. Vijaykrishnan Narayanan
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  6. Chaitali Chakrabarti
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Corresponding author

Correspondence to Chi-Li Yu.

Additional information

This paper is an extension of our paper that appeared in SIPS ’09. The added sections are: (1) Impact of large data size on conventional 2D DFT architecture (Section 2.2); (2) Detailed descriptions of the infrastructure components of the FPGA platform (Section 4.2); (3) Detailed description of the automatic 2D DFT system generator (Section 5); (4) Accuracy analysis of the 2D DFT (Section 6.4).

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Yu, CL., Kim, JS., Deng, L. et al. FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-sized Data. J Sign Process Syst 64, 109–122 (2011). https://doi.org/10.1007/s11265-010-0500-y

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  • DOI: https://doi.org/10.1007/s11265-010-0500-y

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