Abstract
Embedded systems designers often use fixed-point instead of floating-point due to the performance and area overhead of floating-point units. If the range of floating-point representation is required, the system may use a software-based floating-point library on an integer-only processor to save area—at the cost of much lower performance. Instead, we propose a Fractured Floating Point Unit (FFPU)—a hybrid solution that uses a set of custom hardware instructions to accelerate software-based floating-point emulation. An FFPU is intended as a compromise between software libraries and full FPUs in terms of both area and performance. We present four potential 32-bit FFPU designs for a Nios II soft processor. We compare their performance and area to the baseline Nios II, as well as a Nios II with a complete FPU. We show that an FFPU can improve various floating-point operations, including improving addition and subtraction performance by 24 to 52 percent over the baseline. This performance comes at a resource cost of only an 11 to 29 percent ALM increase, and no increase in DSP blocks.
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Notes
The Altera FPU does not include an option for hardware-based square root support.
SoftFloat left-shifts intermediate significands to preserve round, guard, and sticky bits for values stored in integer registers. See the extractSignificand instruction for details.
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Acknowledgments
We would like to thank Altera Corporation and Terasic Technologies for the speedy donation of the DE3 board used in this study, Guy Lemieux for suggesting this type of project, and André DeHon for some useful pointers to related work.
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Hockert, N., Compton, K. Improving Floating-Point Performance in Less Area: Fractured Floating Point Units (FFPUs). J Sign Process Syst 67, 31–46 (2012). https://doi.org/10.1007/s11265-010-0561-y
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DOI: https://doi.org/10.1007/s11265-010-0561-y