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Deployment of Run-Time Reconfigurable Hardware Coprocessors Into Compute-Intensive Embedded Applications

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Abstract

Day after day, embedded systems add more compute-intensive applications inside their end products: cryptography or image and video processing are some examples found in leading markets like consumer electronics and automotive. To face up these ever-increasing computational demands, the use of hardware accelerators synthesized in field-programmable gate arrays (FPGA) lets achieve processing speedups of orders of magnitude versus their counterpart CPU-based software approaches. However, the inherent increment in physical resources penalizes in cost. To address this issue, dynamically reconfigurable hardware technology definitively reached its maturity. SRAM-based reconfigurable logic goes beyond the classical conception of static hardware resources distributed in space and held invariant for the entire application life cycle; it provides a new design abstraction featured by the temporal partitioning of such resources to promote their continuous reuse, reconfiguring them on the fly to play a different role in each instant. This new computing paradigm lets balance the design of embedded applications by partitioning their functionality in space and time—through a series of mutually-exclusive processing tasks synthesized multiplexed in time on the same set of resources—and achieving thus cost savings in both area and power metrics. However, the exploitation of this system versatility requires special attention to avoid performance degradation. Such technical aspects are addressed in this work intended to be a survey on reconfigurable hardware technology and aimed at defining an open, standard and cost-effective system architecture driven by flexible coprocessors instantiated on demand on reconfigurable resources of an FPGA. This concept fits well with the functional features demanded to many embedded applications today and its feasibility has been proved with a state-of-the-art commercial SRAM-based FPGA platform. The achieved results highlight dynamic partial reconfiguration as a potential technology to lead the next computing wave in the industry.

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Authors and Affiliations

  1. Department of Electronic, Electrical and Automatic Control Engineering, Universitat Rovira i Virgili, Tarragona, Spain

    Francisco Fons, Mariano Fons & Enrique Cantó

  2. Department of Electronic Engineering, Universitat Politècnica de Catalunya, Vilanova i la Geltrú, Spain

    Mariano López

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  1. Francisco Fons
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  2. Mariano Fons
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  4. Mariano López
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Correspondence to Mariano Fons.

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Fons, F., Fons, M., Cantó, E. et al. Deployment of Run-Time Reconfigurable Hardware Coprocessors Into Compute-Intensive Embedded Applications. J Sign Process Syst 66, 191–221 (2012). https://doi.org/10.1007/s11265-011-0607-9

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