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An Efficient Block Entropy Based Compression Scheme for Systems-on-a-Chip Test Data

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Abstract

The emergence of the nanometer scale integration technology made it possible for systems-on-a-chip, SoC, design to contain many reusable cores from multiple resources. This resulted in higher complexity SoC testing than the conventional VLSI. To address this increase in design complexity in terms of data-volume and test-time, several compression methods have been developed, employed and proposed in the literature. In this paper, we present a new efficient test vector compression scheme based on block entropy in conjunction with our improved row-column reduction routine to reduce test data significantly. Our results show that the proposed method produces much higher compression ratio than all previously published methods. On average, our scheme scores nearly 13% higher than the best reported results. In addition, our scheme outperformed all results for each of the tested circuits. The proposed scheme is very fast and has considerable low complexity.

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References

  1. El-Maleh, A., Zahir, S., & Khan, E. (2001). A geometric-primitives-based compression scheme for testing systems-on-a-chip. Proc. VLSI Test Symp., Marina Del Rey, CA, pp. 54–59.

  2. El-Maleh, A. (2008). An efficient test compression technique based on block merging. Computers & Digital Techniques, 2(5), 327–335.

    Article  Google Scholar 

  3. Touba, A. N. (2006). Survey of test vector compression techniques. IEEE Design & Test of Computers, 23(4), 294–303.

    Article  Google Scholar 

  4. Gonciari, P. T., Al-Hashimi, B., & Nicolici, N. (2005). Synchronization Overhead in SoC compressed test. IEEE Trans VLSI Systems, 13(1), 140–153.

    Article  Google Scholar 

  5. Balakrishnan, K. J., & Touba, N. A. (2007). Relationship between entropy and test data compression. IEEE Trans Computer-Aided Design of Integrated Circuits and Systems, 26(2), 386–395.

    Article  Google Scholar 

  6. Shannon, C. E. (1948). A mathematical theory of communication. The Bell System Technical Journal, 27, 379–423.

    MathSciNet  MATH  Google Scholar 

  7. Hackett, P. G. (2003). An entropy-based assessment of the unicode encoding for Tibetan. Tibetan Information Technology Panel.

  8. Hamzaoglu, I., & Patel, J. H. (1998). Test set compaction algorithms for combinational circuits (pp. 283–289). San Jose, CA: Proc. Int. Conf. Computer-Aided Design.

    Google Scholar 

  9. Chandra, A., & Chakrabarty, K. (2003). Test data compression and test resource partitioning for system-on-a-chip using Frequency-Directed Run-Length (FDR) codes. IEEE Trans Computer, 52(8), 1076–1088.

    Article  Google Scholar 

  10. El-Maleh, A., & Al-Abaji, R. (2002). Extended frequency-directed run length code with improved application to system-on-a-chip test data compression (pp. 449–452). Dubrovnik: Proc. of the 9th IEEE Int. Conf. on Electronics, Circuits, and Systems.

    Google Scholar 

  11. Jas, A., & Touba, N. A. (1998). Test vector decompression via cyclical scan chains and its application to testing core-based designs. Proc. of Int. Test Conf., pp. 458–464.

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Authors and Affiliations

  1. Image Processing and Graphics Lab, Computer Science Department, UNBC, Prince George, BC, Canada

    Saif Zahir & Arber Borici

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  1. Saif Zahir
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  2. Arber Borici
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Correspondence to Saif Zahir.

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Zahir, S., Borici, A. An Efficient Block Entropy Based Compression Scheme for Systems-on-a-Chip Test Data. J Sign Process Syst 69, 133–142 (2012). https://doi.org/10.1007/s11265-011-0635-5

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  • DOI: https://doi.org/10.1007/s11265-011-0635-5

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