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Efficient 45nm ASIC Architecture for Full-Search Free Intra Prediction in Real-Time H.264/AVC Decoder

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Abstract

The standard H.264/AVC Intra frame encoding process has several data dependent and computational intensive coding methodologies that limit the overall encoding speed. It causes not only a high degree of computational complexity but also an unacceptable delay especially for the real-time video applications. Based on DCT properties and spatial activity analysis, low power hardware architecture for high throughput Full-Search Free (FSF) Intra mode selection and direction prediction algorithm is proposed. The FSF Intra prediction Algorithm significantly reduces the computational complexity and the processing run-time required for the H.264/AVC Intra frame prediction process. The ASIC implementation for the proposed architecture is carried out and synthesizing results are obtained. The heavily tested 45nm ASIC design is able to achieve an operating frequency of 140 MHz while limiting the overall power consumption to 9.01 mW, which nominates our proposed FSF Intra prediction architecture for interactive real-time H.264/AVC mobile video decoders.

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Authors and Affiliations

  1. The Center for Advanced Computer Studies (CACS), University of Louisiana at Lafayette, Lafayette, LA, USA

    Tarek A. Elarabi, Randa Ayoubi, Hanan Mahmoud & Magdy A. Bayoumi

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  1. Tarek A. Elarabi
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  2. Randa Ayoubi
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  3. Hanan Mahmoud
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  4. Magdy A. Bayoumi
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Correspondence to Tarek A. Elarabi.

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Elarabi, T.A., Ayoubi, R., Mahmoud, H. et al. Efficient 45nm ASIC Architecture for Full-Search Free Intra Prediction in Real-Time H.264/AVC Decoder. J Sign Process Syst 70, 91–104 (2013). https://doi.org/10.1007/s11265-012-0700-8

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  • DOI: https://doi.org/10.1007/s11265-012-0700-8

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