Abstract
For high-mobility 4G applications of LTE-A and WiMAX-2 systems, this paper presents a dual-standard turbo decoder design with the following three techniques. 1) Circular parallel decoding reduces decoding latency and improves throughput rate. 2) Collision-free vectorizable dual-standard parallel interleaver enhances hardware utilization of the interleaving address generator. 3) One-bank extrinsic buffer design with bit-level extrinsic information exchange reduces size of the extrinsic buffer compared with the two-bank extrinsic buffer design. Furthermore, a multi-standard turbo decoder chip is fabricated in a core area of 3.38 mm2 by 90 nm CMOS process. This chip is maximally measured at 152 MHz with 186.1 Mbps for LTE-A standard and 179.3 Mbps for WiMAX-2 standard.
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The authors would like to thank Chip Implementation Center (CIC) for the support of chip fabrication.
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This work was supported in part by National Science Council, R.O.C., under grants NSC 99-2218-E-155-011 and NSC 97-2220-E-002-012. The material in this paper was presented in part at the IEEE ISIC 2011, Singapore.
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Lin, CH., Chen, CY., Chang, EJ. et al. Reconfigurable Parallel Turbo Decoder Design for Multiple High-Mobility 4G Systems. J Sign Process Syst 73, 109–122 (2013). https://doi.org/10.1007/s11265-013-0735-5
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DOI: https://doi.org/10.1007/s11265-013-0735-5