Skip to main content
Log in

Decimal Division Algorithms: The Issue of Partial Remainders

  • Published:
Journal of Signal Processing Systems Aims and scope Submit manuscript

Abstract

The efficiency of decimal digit-recurrence division algorithms is totally affected by the number representations of the quotient, the divisor and partial remainders participated in quotient digit selection (QDS). This paper establishes general rules and conditions for QDS with operands represented in the generalized signed-digit format. As a result of this generalization, a universal convergence condition is introduced which obviates the unnecessary conservatism of previous algorithms and hence paves the way for more correct and efficient decimal division hardware designs. It is also concluded that keeping the partial remainders in minimally redundant symmetric signed-digit representation (with digit-set [−5,6])and applying into QDS the divisor represented in minimally asymmetric non-redundant signed-digit format (with digit-set [−4,5]) lead to the smallest minimum precision required, of the divisor and the partial remainder, for QDS and thus faster and simpler division algorithm. Moreover, it is shown that even in case of using non-redundant partial remainders (for the sake of lower area cost); minimally asymmetric signed-digit representation brings about more efficiency. The suggested representations are applied to the fastest previous decimal digit-recurrence divider and 10 % speed-up is achieved while keeping the area cost approximately unaltered.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Figure 1
Figure 2
Figure 3
Figure 4
Figure 5

Similar content being viewed by others

References

  1. Butts, J.A., Tang, P.T.P, Dror, R.O., Shaw, D.E. (2011). Radix-8 digit-by-rounding: achieving high-performance reciprocals, square roots, and reciprocal square roots. In Proceedings of 20 th IEEE Symposium on Computer Arithmetic (ARITH20), pp. 149–158.

  2. Ercegovac, M.D. (1983). A higher-radix division with simple selection of quotient digits. In Proceedings of 6 th IEEE Symposium on Computer Arithmetic (ARITH6), pp. 94–98.

  3. Ercegovac, M. D., & Lang, T. (2004). Digital arithmetic. Burlington: Morgan Kaufmann Publishers.

    Google Scholar 

  4. IEEE Standards Committee (2008). 754-2008 IEEE standard for floating-point arithmetic. pp. 1–58. doi:10.1109/IEEESTD.2008.4610935.

  5. Jaberipur, G., Parhami, B., & Ghodsi, M. (2005). Weighted two-valued digit-set encodings: unifying efficient hardware representation schemes for redundant number systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 52(7), 1348–1357.

    Article  MathSciNet  Google Scholar 

  6. Kaivani, A., Hosseiny, A., & Jaberipur, G. (2011). Improving the speed of decimal division. IET Computer & Digital Techniques, 5(5), 393–404.

    Article  Google Scholar 

  7. Kornerup, P. (2005). Digit selection for SRT division and square root. IEEE Transactions on Computers, 54(3), 294–303.

    Article  MathSciNet  Google Scholar 

  8. Lang, T., & Nannarelli, A. (2007). A radix-10 digit-recurrence division unit: algorithm and architecture. IEEE Transactions on Computers, 56(6), 727–739.

    Article  MathSciNet  Google Scholar 

  9. Montuschi, P., & Ciminiera, L. (1994). Over-redundant digit sets and the design of digit-by-digit division units. IEEE Transactions on Computers, 43(3), 269–277.

    Article  Google Scholar 

  10. Parhami, B. (1990). Generalized signed-digit number systems: a unifying framework for redundant number representations applications. IEEE Transactions on Computers, 39(1), 89–98.

    Article  Google Scholar 

  11. Parhami, B. (1993). On the implementation of arithmetic support functions for generalized signed-digit number systems. IEEE Transactions on Computers, 42(3), 379–384.

    Article  Google Scholar 

  12. Parhami, B. (2001). Precision requirements for quotient digit selection in high-radix division. Proceedings of 35 th Asilomar Conference on Circuits, Systems, and Computers, pp. 1670–1673.

  13. Parhami, B. (2003). Tight upper bounds on the minimum precision required of the divisor and the partial remainder in high-radix division. IEEE Transactions on Computers, 52(11), 1509–1514.

    Article  Google Scholar 

  14. Schwarz, E. M., & Carlough, S.R. (2007). Power6 decimal divide. Proc. IEEE Int. Conf. Appl.-Specific Syst., Arch., Processors (ASAP), pp. 128–133.

  15. STMicroelectronics (2007) 90 nm CMOS090 design platform.

  16. Tang, P.T.P., Butts, J.A., Dror, R.O., Shaw, D.E. (2011). Tight certification techniques for digit-by-rounding algorithms with application to a new \( \frac{1}{\sqrt{x}} \) design. In Proceedings of 20 th IEEE Symposium on Computer Arithmetic (ARITH20), pp. 159–168.

  17. Vazquez, A.A., & Montuschi, E.P. (2007). A radix-10 SRT divider based on alternative BCD codings. XXV IEEE International Conference on Computer Design (ICCD 2007), Lake Tahoe, CA, pp. 280–287.

  18. Vazquez, A. (2009). High-performance decimal floating-point units. Ph.D. Dissertation, Universidade De Santiago De Compostela, Spain.

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Seok-Bum Ko.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Kaivani, A., Ko, SB. Decimal Division Algorithms: The Issue of Partial Remainders. J Sign Process Syst 73, 181–188 (2013). https://doi.org/10.1007/s11265-013-0742-6

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11265-013-0742-6

Keywords

Navigation