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Performance Characterization of AES Datapath Architectures in 90-nm Standard Cell CMOS Technology

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Abstract

In this paper, we characterize the performance of datapath architectures of the Advanced Encryption Standard (AES). These architectures are parameterized by a datapath width of 8, 16, 32, 64, or 128 bits and, for the 128-bit width, an unrolling factor of 1, 2, 5 or 10. Composite field S-boxes are adopted for all the architectures and shift registers based ShiftRows and MixColumns components are used for architectures with datapath widths of less than 128 bits. Their performance in terms of area, peak power and average energy is benchmarked using a 90-nm standard cell CMOS technology under a variety of throughput requirements. Through this characterization, the performance trade-offs affected by the architecture parameters are extensively explored. The parameters leading to the best performance are identified. It is found that the 8-bit width datapath, which is conventionally adopted for resource efficient purposes, has the worst energy efficiency and does not result in the minimal peak power among the architectures. As well, the 16, 32 and 64-bit width AES datapath architectures are newly considered or represent improvements over previous work.

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Acknowledgments

This work was funded by the Natural Sciences and Engineering Research Council of Canada (NSERC) and facilitated by tools provided by CMC Microsystems.

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Authors and Affiliations

  1. Faculty of Engineering, Memorial University of Newfoundland, St. Johns, NL, A1B 3X5, Canada

    Cheng Wang & Howard M. Heys

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  1. Cheng Wang
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Correspondence to Howard M. Heys.

Appendices

Appendix A: Description of the Operationof the ShiftRows Components

The operation of the ShiftRows components shown in Fig. 3 is controlled through the multiplexers. All the 8-bit registers are driven with a continuous clock. In order to demonstrate the operation of these components, the contents of the registers at some selected clock cycles are shown in Tables 10, 11, 12 and 13 for Fig. 3a, b, c and d, respectively, where the first clock cycle is denoted as CC00 and the p-th clock cycle after CC00 is denoted as CCp. The content of a register is a byte of the State following the notation in Fig. 1, where the primed State bytes represent values following the application of the ShiftRows operation.

Table 10 Contents of the registers of the 8-bit width ShiftRows component at the selected clock cycles.
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Table 11 Contents of the registers of the 16-bit width ShiftRows component at the selected clock cycles.
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Table 12 Contents of the registers of the 32-bit width ShiftRows component at the selected clock cycles.
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Table 13 Contents of the registers of the 64-bit width ShiftRows component at the selected clock cycles.
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Appendix B: Description of the Operationof the MixColumns Components

The operation of the MixColumns components shown in Fig. 4 is controlled through the multiplexers and the AND gates. All the 8-bit registers are driven with a continuous clock. In order to demonstrate the operation of these components, the contents of the registers at the clock cycles of an operation are shown in Tables 14, 15 and 16 for Fig. 4a, b and c, respectively, where the first clock cycle is denoted as CC00 and the p-th clock cycle after CC00 is denoted as CCp. The content of a register is a byte following the notation in (1).

Table 14 Contents of the registers of the 8-bit width MixColumns component for the clock cycles during a complete operation (\(m=n+1\)).
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Table 15 Contents of the registers of the 16-bit width MixColumns component for the clock cycles during a complete operation (\(m=n+1\)).
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Table 16 Contents of the registers of the 32-bit width MixColumns component for the clock cycles during a complete operation.
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Wang, C., Heys, H.M. Performance Characterization of AES Datapath Architectures in 90-nm Standard Cell CMOS Technology. J Sign Process Syst 75, 217–231 (2014). https://doi.org/10.1007/s11265-013-0788-5

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  • DOI: https://doi.org/10.1007/s11265-013-0788-5

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