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VLSI Design of FM0/Manchester Encoder with Reuse-Oriented Boolean Simplification Technique for DSRC Applications

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Abstract

The Dedicated Short-Range Communication (DSRC) is an emerging standard to push the vehicular communication into modern automotive industry. The DSRC standard generally applies FM0 and Manchester to reach DC-balance enhancing the signal reliability. However, the intrinsic unbalance computation load between FM0 and Manchester makes their VLSI architecture with poor hardware utilization. In this paper, the reuse-oriented Boolean simplification (ROBS) technique is proposed to overcome this problem. The ROBS technique constructs the balance-type architecture to improve the hardware utilization rate (HUR) from 50 % to 90 %. The analysis of how the clock-skew affects the balance-type architecture is also discussed. This work is realized by 0.18um 1P6M CMOS technology with cell-based design flow. The gate count is 25.61, which is normalized to a 2-input NAND gate. The power consumption is 6.58uW@27MHz for FM0 encoding and 6.85uW@27MHz for Manchester encoding. The encoding capability is up to 27 Mbps that can fully support the DSRC standards of America, Europe and Japan.

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Acknowledgments

This work is supported in part by National Science Council (NSC), Republic of China, Taiwan, under the grant number NSC 99-2218-E-155-012, NSC 101-2221-E-155-072 and NSC 100-2220-E-155-006. Many thanks for NSC and Chip Implementation Center (CIC) for their support.

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  1. 135 Yuan-Tung Road, Chung-Li, 32003, Taoyuan, Taiwan, Republic of China

    Yu-Hsuan Lee & Cheng-Wei Pan

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  1. Yu-Hsuan Lee
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  2. Cheng-Wei Pan
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Correspondence to Yu-Hsuan Lee.

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Lee, YH., Pan, CW. VLSI Design of FM0/Manchester Encoder with Reuse-Oriented Boolean Simplification Technique for DSRC Applications. J Sign Process Syst 78, 199–208 (2015). https://doi.org/10.1007/s11265-013-0815-6

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  • DOI: https://doi.org/10.1007/s11265-013-0815-6

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