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Coarse-grained Dynamically Reconfigurable Processor for Vision Pre-Processing

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Abstract

The operations in vision pre-processing, especially two-dimensional convolution, are computation-intensive and demand high flexibility. Reconfigurable hardware has been typically used to achieve a good trade-off between performance and flexibility. A coarse-grained dynamically reconfigurable processor is presented for vision pre-processing. The processor architecture is a combination of a hardware reconfiguration controller, a color space converter, a reconfigurable convolution array, a convolution post-processing module, and a sampling and storing module. The dynamic reconfiguration approach and coarse-grained architecture can improve the performance and flexibility of the processor. The reconfigurable convolution array, which is the main component of the processor, can simultaneously perform convolutions with different masks, with the maximum mask size up to 16 × 16. The hardware reconfiguration controller can shorten the reconfiguration time and reduce the application difficulty. The processor is implemented on an FPGA. Experimental results show that the frame rate of the processor is more than 150 fps, far exceeding the real-time requirement for the vision system. Synthesis results show that the processor can deliver 87.1 GOPS and 3.95 GOPS/mm2 at 140 MHz system clock in SMIC 0.18μm CMOS process. The simulation and experimental results demonstrate that the processor is applicable to real-time vision pre-processing.

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Acknowledgments

This work is supported by National Natural Science Foundation of China (61231018 and 60905007) and Ministry of education program for New Century Excellent Talents (NCET-11- 0427).

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Authors and Affiliations

  1. Xi’an Jiaotong University, Xi’an, Shaanxi, China

    Bin Zhang, Kuizhi Mei & Nanning Zheng

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  1. Bin Zhang
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  2. Kuizhi Mei
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  3. Nanning Zheng
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Correspondence to Bin Zhang.

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Zhang, B., Mei, K. & Zheng, N. Coarse-grained Dynamically Reconfigurable Processor for Vision Pre-Processing. J Sign Process Syst 79, 45–61 (2015). https://doi.org/10.1007/s11265-013-0828-1

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  • DOI: https://doi.org/10.1007/s11265-013-0828-1

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