Abstract
Wavelet transform has contributed significantly in multiple areas such as image processing, compression, signal analysis, and medical imaging. Discrete wavelet transform (DWT) requires very large memory requirement and is computationally intensive, especially for 2-D transform that has a quadratic computational complexity. In this paper, we propose a dedicated processor for 2-D DWT computation. The DWT system architecture is parameterizable, where its performance can be scaled by increasing or reducing the DWT engines, according to different application needs. This architecture requires significantly less computational resources and internal memory. The proposed architecture can achieve a theoretical throughput of 138 frames per second for a 2048 × 1536 video processing. The DWT system has been designed for scalability to support up to 8 parallel DWT engines.
Similar content being viewed by others
References
Andra, K., Chakrabarti, C., Acharya, T. (2002). A VLSI architecture for lifting-based forward and inverse wavelet transform. IEEE Transaction on Signal Processing, 50(4), 966–977.
Benderli, O. (2003). A real-time, low-latency, FPGA implementation of the two dimensional discrete wavelet transform. M.sc. thesis: The Graduate School of Natural and Applied Sciences of The Middle East Technical University.
Chakrabarti, C., & Vishwanath, M. (1995). Efficient realizations of the discrete and continuous wavelet transforms: from single chip implementations to mappings on SIMD array computers. IEEE Transactions on Signal Processing, 43(3), 759–771.
Chakrabarti, C., Vishwanath, M., Owens, R. M. (1993). Architectures for wavelet transform. In Proceedings of the 1993 IEEE workshop on vlsi signal processing (pp. 507–515). Netherlands: Veldhoven.
Huang, C. T., Tseng, P. C., Chen, L. G. (2004). Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform. IEEE Transactions on Signal Processing, 52(4), 1080–1089.
Jamkhandi, P., Mukherjee, A., Mukherjee, K., Franceschini, R. (2000). Parallel hardware software architecture for computation of discrete wavelet transform using the recursive merge filtering algorithm. In International Parallel and Distributed Processing Symposium Workshop (pp. 250–256). Mexico: Cancun.
Mallat, S. G. (1989). A theory for multiresolution signal decomposition: the wavelet representation. IEEE Transactions on Pattern Analysis and Machine Intelligence, 11(7), 674–693.
Mansouri, A., Ahaitouf, A., Abdi, F. (2009). An efficient VLSI architecture and FPGA implementation of high-speed and low power 2-D DWT for (9, 7) wavelet filter. IJCSNS International Journal of Computer Science and Network Security, 9(3), 50–60.
Martina, M., Masera, G., Piccinini, G., Zamboni, M. (2000). A VLSI architecture for IWT (Integer Wavelet Transform). In Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (pp. 1174–1177). USA: Lansing.
Sweldens, W. (1996). The lifting scheme: a custom-design construction of biorthogonal wavelets. Applied and Computational Harmonic Analysis, 3(15), 186–200.
Vishwanath, M., Owens, R. M., Irwin, M. (1995). VLSI architectures for the discrete wavelet transform. IEEE Transactions on Circuits and Systems, 42(5), 305–316.
Wu, B. F., & Lin, C. F. (2003). A rescheduling and fast pipeline VLSI architecture for lifting-based discrete wavelet transform. In Proceedings of the 2003 IEEE International Symposium on Circuits and Systems (ISCAS 2003), vol. 2, pp. II–732 – II–735. Bangkok.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Ang, B.H., Sheikh, U.U. & Marsono, M.N. 2-D DWT System Architecture for Image Compression. J Sign Process Syst 78, 131–137 (2015). https://doi.org/10.1007/s11265-013-0834-3
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11265-013-0834-3